John P. Keane

According to our database, John P. Keane authored at least 10 papers between 2002 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC).

David T. Blaauw, Hoi Lee, John P. Keane, Jaehyouk Choi, Sudhakar Pamarti

IEEE J. Solid State Circuits, 2020

2017

16.5 An 8GS/s time-interleaved SAR ADC with unresolved decision detection achieving -58dBFS noise and 4GHz bandwidth in 28nm CMOS.

John P. Keane, Nathaniel J. Guilar, Dusan Stepanovic, Bernd Wuppermann, Charles Wu, Cheongyuen W. Tsang, Robert Neff, Ken Nishimura

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2015

An Integrator-Based Pipelined ADC With Digital Calibration.

Dong Wang, John P. Keane, Paul J. Hurst, Stephen H. Lewis

IEEE Trans. Circuits Syst. II Express Briefs, 2015

2013

A 14b 2.5GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction.

Brian Setterberg, Ken Poulton, Sourja Ray, Dan J. Huber, Valentin Abramzon, Guenter Steinbach, John P. Keane, Bernd Wuppermann, Mathew Clayson, Matthew Martin, Rizwan Pasha, Edda Peeters, Annemie Jacobs, Filip Demarsin, Adnan Al-Adnani, Peter Brandt

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2006

Digital background calibration for memory effects in pipelined analog-to-digital converters.

John P. Keane, Paul J. Hurst, Stephen H. Lewis

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

2005

Background interstage gain calibration technique for pipelined ADCs.

John P. Keane, Paul J. Hurst, Stephen H. Lewis

IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Convergence analysis of a background interstage gain calibration technique for pipelined ADCs.

Dong Wang, John P. Keane, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers.

Paul J. Hurst, Stephen H. Lewis, John P. Keane, Farbod Aram, Kenneth C. Dyer

IEEE Trans. Circuits Syst. I Regul. Pap., 2004

2003

Analog timing recovery for a noise-predictive decision-feedback equalizer.

John P. Keane, Michael Q. Le, Paul J. Hurst

IEEE J. Solid State Circuits, 2003

2002

An adaptive analog noise-predictive decision-feedback equalizer.

Michael Q. Le, Paul J. Hurst, John P. Keane

IEEE J. Solid State Circuits, 2002