John Moondanos

According to our database, John Moondanos authored at least 16 papers between 1992 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

A power-supply noise aware dynamic timing analysis methodology, based on a statistical prediction engine.

Michael K. Tsiampas, Nestor E. Evmorfopoulos, Konstantis Daloukas, John Moondanos, Georgios I. Stamoulis

Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

2010

Characterization of the worst-case current waveform excitations in general RLC-model power grid analysis.

Nestoras E. Evmorfopoulos, Maria-Aikaterini Rammou, George I. Stamoulis, John Moondanos

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

2007

An Efficient Diagnostic Test Pattern Generation Framework Using Boolean Satisfiability.

Feijun Zheng, Kwang-Ting Cheng, Xiaolang Yan, John Moondanos, Ziyad Hanna

Proceedings of the 16th Asian Test Symposium, 2007

2006

From Error to Error: Logic Debugging in the Many-Core Era.

John Moondanos

Proceedings of the Workshop on Verification and Debugging, 2006

Generation of shorter sequences for high resolution error diagnosis using sequential SAT.

Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

JPEG Encoding on the Intel MXP5800: A Platform-Based Design Case Study.

Abhijit Davare, Qi Zhu, John Moondanos, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005

2004

A Signal Correlation Guided Circuit-SAT Solver.

Feng Lu, Li-C. Wang, Kwang-Ting (Tim) Cheng, John Moondanos, Ziyad Hanna

J. Univers. Comput. Sci., 2004

Preserving synchronizing sequences of sequential circuits after retiming.

Maher N. Mneimneh, Karem A. Sakallah, John Moondanos

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

A signal correlation guided ATPG solver and its applications for solving difficult industrial cases.

Feng Lu, Li-C. Wang, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna

Proceedings of the 40th Design Automation Conference, 2003

2002

TRANS: efficient sequential verification of loop-free circuits.

Zurab Khasidashvili, John Moondanos, Ziyad Hanna

Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

2001

An enhanced cut-points algorithm in formal equivalence verification.

Zurab Khasidashvili, John Moondanos, Daher Kaiss, Ziyad Hanna

Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination.

John Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss

Proceedings of the Computer Aided Verification, 13th International Conference, 2001

1997

Automatic verification of implementations of large circuits against HDL specifications.

Yatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell, John Moondanos

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

1994

Verification of Circuits Described in VHDL through Extraction of Design Intent.

Yatin Vasant Hoskote, John Moondanos, Jacob A. Abraham, Donald S. Fussell

Proceedings of the Seventh International Conference on VLSI Design, 1994

Abstraction of data path registers for multilevel verification of large circuits.

Yatin Vasant Hoskote, John Moondanos, Jacob A. Abraham, Donald S. Fussell

Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

1992

Sequential Redundancy Identification Using Verification Techniques.

John Moondanos, Jacob A. Abraham

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992