John Marty Emmert

Orcid: 0000-0002-6074-535X

According to our database1, John Marty Emmert authored at least 38 papers between 1997 and 2024.

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Bibliography

2024
Research and Development Priorities for Security of Embedded Hardware Devices.
IEEE Trans. Engineering Management, 2024

A Survey of Electromagnetic Radiation Based Hardware Assurance and Reliability Monitoring Methods in Integrated Circuits.
IEEE Access, 2024

A Second Look at the Portability of Deep Learning Side-Channel Attacks over EM Traces.
Proceedings of the 27th International Symposium on Research in Attacks, 2024

TinyPower: Side-Channel Attacks with Tiny Neural Networks.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024

2023
Portability of Deep-Learning Side-Channel Attacks against Software Discrepancies.
Proceedings of the 16th ACM Conference on Security and Privacy in Wireless and Mobile Networks, 2023

RELUT-GNN: Reverse Engineering Data Path Elements From LUT Netlists Using Graph Neural Networks.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Reverse Engineering of RTL Controllers from Look-Up Table Netlists.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

TripletPower: Deep-Learning Side-Channel Attacks over Few Traces.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2023

Gotcha! I Know What You Are Doing on the FPGA Cloud: Fingerprinting Co-Located Cloud FPGA Accelerators via Measuring Communication Links.
Proceedings of the 2023 ACM SIGSAC Conference on Computer and Communications Security, 2023

2022
THx2 Programmable Logic Block Architecture for Clockless Asynchronous FPGAs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Hardware Trojan Detection Through Multimodal Image Processing and Analysis.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

Area Efficient Asynchronous Circuits for Side Channel Attack Mitigation.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

2021
Fully BEOL-Compatible Switch Boxes Using RRAMs and Thin Film Transistors for Reconfigurable and Secure ICs.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

Educating the Next Generation of Cybersecurity Defenders at the University of Cincinnati.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

EMC: Efficient Muller C-Element Implementation for High Bit-width Asynchronous Applications.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

2020
An Asynchronous FPGA THx2 Programmable Cell for Mitigating Side-Channel Attacks.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

2007
Online Fault Tolerance for FPGA Logic Blocks.
IEEE Trans. Very Large Scale Integr. Syst., 2007

2006
A survey of fault tolerant methodologies for FPGAs.
ACM Trans. Design Autom. Electr. Syst., 2006

2004
Online BIST and BIST-based diagnosis of FPGA logic blocks.
IEEE Trans. Very Large Scale Integr. Syst., 2004

2003
On Using Tabu Search for Design Automation of VLSI Systems.
J. Heuristics, 2003

An FFT Approximation Technique Suitable for On-Chip Generation and Analysis of Sinusoidal Signals.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

A Monolithic Spectral BIST Technique for Control or Test of Analog or Mixed-Signal Circuits.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002
Using embedded FPGAs for SoC yield improvement.
Proceedings of the 39th Design Automation Conference, 2002

2001
Two-dimensional Placement Using Tabu Search.
VLSI Design, 2001

On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

Roving Stars: An Integrated Approach To On-Line Testing, Diagnosis, And Fault Tolerance For Fpgas In Adaptive Computing Systems.
Proceedings of the 3rd NASA / DoD Workshop on Evolvable Hardware (EH 2001), 2001

On-Line Incremental Routing for Interconnect Fault Tolerance in FPGAs Minus the Router .
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

On-Line Fault Tolerance for FPGA Interconnect with Roving STARs.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000
A Fault Tolerant Technique for FPGAs.
J. Electron. Test., 2000

Bridging fault extraction from physical design data for manufacturing test development.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Improving On-Line BIST-Based Diagnosis for Roving STARs.
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

Performance Penalty for Fault Tolerance in Roving STARs.
Proceedings of the Field-Programmable Logic and Applications, 2000

Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

1999
Fast timing driven placement using tabu search.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Tabu Search: Ultra-Fast Placement for FPGAs.
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

A Methodology for Fast FPGA Floorplanning.
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

1998
Fast Floorplanning for FPGAs.
Proceedings of the Field-Programmable Logic and Applications, 1998

1997
Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement.
Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997


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