John Lillis

According to our database, John Lillis authored at least 32 papers between 1995 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2017

Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation.

Marco Rabozzi, Gianluca Carlo Durelli, Antonio Miele, John Lillis, Marco Domenico Santambrogio

IEEE Trans. Very Large Scale Integr. Syst., 2017

2014

Floorplanning for Partially-Reconfigurable FPGA Systems via Mixed-Integer Linear Programming.

Marco Rabozzi, John Lillis, Marco D. Santambrogio

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

2008

Generalized Buffer Insertion.

Milos Hrkic, John Lillis

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

A Layout-Level Logic Restructuring Framework for LUT-Based FPGAs.

Hosung Kim, John Lillis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A framework for layout-level logic restructuring.

Hosung (Leo) Kim, John Lillis

Proceedings of the 2008 International Symposium on Physical Design, 2008

2007

RBI: Simultaneous Placement and Routing Optimization Technique.

Devang Jariwala, John Lillis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Repeater insertion for concurrent setup and hold time violations with power-delay trade-off.

Salim Chowdhury, John Lillis

Proceedings of the 2007 International Symposium on Physical Design, 2007

Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space.

Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng, John Lillis

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

An Approach to Placement-Coupled Logic Replication.

Milos Hrkic, John Lillis, Giancarlo Beraudo

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Trunk decomposition based global routing optimization.

Devang Jariwala, John Lillis

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Techniques for improved placement-coupled logic replication.

Hosung (Leo) Kim, John Lillis, Milos Hrkic

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

2005

A study of tighter lower bounds in LP relaxation based placement.

Qingzhou (Ben) Wang, Devang Jariwala, John Lillis

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

An LP-based methodology for improved timing-driven placement.

Qingzhou (Ben) Wang, John Lillis, Shubhankar Sanyal

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

On interactions between routing and detailed placement.

Devang Jariwala, John Lillis

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2003

Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockages.

Milos Hrkic, John Lillis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Timing optimization of FPGA placements by logic replication.

Giancarlo Beraudo, John Lillis

Proceedings of the 40th Design Automation Conference, 2003

2002

Relaxation and Clustering in a Local Search Framework: Application to Linear Placement.

Sung-Woo Hur, John Lillis

VLSI Design, 2002

A fast algorithm for context-aware buffer insertion.

Ashok Jagannathan, Sung-Woo Hur, John Lillis

ACM Trans. Design Autom. Electr. Syst., 2002

Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages.

Milos Hrkic, John Lillis

Proceedings of 2002 International Symposium on Physical Design, 2002

S-Tree: a technique for buffered routing tree synthesis.

Milos Hrkic, John Lillis

Proceedings of the 39th Design Automation Conference, 2002

2001

Buffered Steiner trees for difficult instances.

Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia

Proceedings of the 2001 International Symposium on Physical Design, 2001

2000

Timing-driven maze routing.

Sung-Woo Hur, Ashok Jagannathan, John Lillis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

MONGREL: Hybrid Techniques for Standard Cell Placement.

Sung-Woo Hur, John Lillis

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

1999

Timing optimization for multisource nets: characterization andoptimal repeater insertion.

John Lillis, Chung-Kuan Cheng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

1998

Table-Lookup Methods for Improved Performance-Driven Routing.

John Lillis, Premal Buch

Proceedings of the 35th Conference on Design Automation, 1998

1997

Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion.

John Lillis, Chung-Kuan Cheng

Proceedings of the 34st Conference on Design Automation, 1997

A new layout-driven timing model for incremental layout optimization.

Fang-Jou Liu, John Lillis, Chung-Kuan Cheng

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

Optimal wire sizing and buffer insertion for low power and a generalized delay model.

John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin

IEEE J. Solid State Circuits, 1996

Simultaneous Routing and Buffer Insertion for High Performance Interconnect.

John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing.

John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin, Chin-Yen Ho

Proceedings of the 33st Conference on Design Automation, 1996

New Spectral Linear Placement and Clustering Approach.

Jianmin Li, John Lillis, Lung-Tien Liu, Chung-Kuan Cheng

Proceedings of the 33st Conference on Design Automation, 1996

1995

Linear decomposition algorithm for VLSI design applications.

Jianmin Li, John Lillis, Chung-Kuan Cheng

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995