John Keane
Affiliations:- Intel Corporation, Hillsboro, OR, USA
- University of Minnesota, Minneapolis, MN, USA (PhD 2010)
According to our database1,
John Keane
authored at least 27 papers
between 2006 and 2017.
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Bibliography
2017
5.6 Mb/mm<sup>2</sup> 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology.
IEEE J. Solid State Circuits, 2017
2016
A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry.
IEEE J. Solid State Circuits, 2016
17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
A 0.094um<sup>2</sup> high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist.
Proceedings of the Symposium on VLSI Circuits, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
IEEE Micro, 2014
A test circuit based on a ring oscillator array for statistical characterization of Plasma-Induced Damage.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry.
IEEE J. Solid State Circuits, 2013
2012
An array-based Chip Lifetime Predictor macro for gate dielectric failures in core and IO FETs.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012
2011
An Array-Based Test Circuit for Fully Automated Gate Dielectric Breakdown Characterization.
IEEE Trans. Very Large Scale Integr. Syst., 2011
An Array-Based Odometer System for Statistically Significant Circuit Aging Characterization.
IEEE J. Solid State Circuits, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Microelectron. Reliab., 2010
IEEE J. Solid State Circuits, 2010
2009
Fuer Chris H. Kim 2 Eintraege in Db, Chris H. Kim und Chris Kim. Identisch. Siehe EE-Links: Univ. of Minnesota. Modeling, Analysis, and Application of Leakage Induced Damping Effect for Power Supply Integrity.
IEEE Trans. Very Large Scale Integr. Syst., 2009
Sleep Transistor Sizing and Adaptive Control for Supply Noise Minimization Considering Resonance.
IEEE Trans. Very Large Scale Integr. Syst., 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property.
IEEE Trans. Very Large Scale Integr. Syst., 2008
A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing.
IEEE J. Solid State Circuits, 2008
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing.
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006