John K. DeBrosse
According to our database1,
John K. DeBrosse
authored at least 11 papers
between 1995 and 2015.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2015
A fully-functional 90nm 8Mb STT MRAM demonstrator featuring trimmed, reference cell-based sensing.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2006
2005
IEEE J. Solid State Circuits, 2005
2004
IEEE J. Solid State Circuits, 2004
2002
Challenges and future directions for the scaling of dynamic random-access memory (DRAM).
IBM J. Res. Dev., 2002
2000
A 7F<sup>2</sup> cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs.
IEEE J. Solid State Circuits, 2000
1998
A 220-mm<sup>2</sup>, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture.
IEEE J. Solid State Circuits, 1998
1997
1996
IEEE J. Solid State Circuits, 1996
1995