John J. Wuu

According to our database, John J. Wuu authored at least 6 papers between 2002 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

AMD Instinct™ MI300X Accelerator: Packaging and Architecture Co-Optimization.

Alan Smith, Gabriel H. Loh, John J. Wuu, Samuel Naffziger, Tyrone Huang, Hugh McIntyre, Ramon Mangaser, Wonjun Jung, Raja Swaminathan

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

11.1 AMD InstinctTM MI300 Series Modular Chiplet Package - HPC and AI Accelerator for Exa-Class Systems.

Alan Smith, Eric Chapman, Chintan Patel, Raja Swaminathan, John J. Wuu, Tyrone Huang, Wonjun Jung, Alexander Kaganov, Hugh McIntyre, Ramon Mangaser

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2022

3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU.

John J. Wuu, Rahul Agarwal, Michael Ciraula, Carl Dietz, Brett Johnson, Dave Johnson, Russell Schreiber, Raja Swaminathan, Will Walker, Samuel Naffziger

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2011

An 8MB level-3 cache in 32nm SOI with column-select aliasing.

Don Weiss, Michael Dreesen, Michael Ciraula, Carson Henrion, Chris Helt, Ryan Freese, Tommy Miles, Anita Karegar, Russell Schreiber, Bryan Schneller, John J. Wuu

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2009

A 2ns-read-latency 4Mb embedded floating-body memory macro in 45nm SOI technology.

Anant Singh, Michael Ciraula, Don Weiss, John J. Wuu, Philippe Bauser, Paul de Champs, Hamid Daghighian, David E. Fisch, Philippe Graber, Michel Bron

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2002

The on-chip 3-MB subarray-based third-level cache on an Itanium microprocessor.

Don Weiss, John J. Wuu, Victor Chin

IEEE J. Solid State Circuits, 2002