John Griesemer

According to our database, John Griesemer authored at least 3 papers between 2005 and 2008.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2008

A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier.

John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer

IEEE J. Solid State Circuits, 2008

2007

A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier.

John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005

An 800-MHz embedded DRAM with a concurrent refresh mode.

Toshiaki Kirihata, Paul C. Parries, David R. Hanson, Hoki Kim, John Golz, Gregory Fredeman, Raj Rajeevakumar, John Griesemer, Norman Robson, Alberto Cestero, Babar A. Khan, Geng Wang, Matt Wordeman, Subramanian S. Iyer

IEEE J. Solid State Circuits, 2005