John G. Kauffman

Orcid: 0000-0003-3840-6885

According to our database¹, John G. Kauffman authored at least 40 papers between 2011 and 2024.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

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On csauthors.net:

Bibliography

2024

A 470μW, 102.6dB-DR, 20kHz BW Calibration-Free ΔΣ Modulator with SFDR in Excess of 110dBc using an Intrinsically Linear 13-Level DAC.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Non-Ideal Reset in Incremental Delta-Sigma ADCs.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE Interregional NEWCAS Conference, 2024

Confidence Estimation and Boosting for Dynamic-Comparator Transient-Noise Analysis.

[BibT_eX]

[DOI]

Vasileios Belagiannis

Maurits Ortmanns

Proceedings of the 22nd IEEE Interregional NEWCAS Conference, 2024

A 600MS/s 10-bit SAR ADC with unit via-based delta-length C-DAC in 22nm FDSOI.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

DAC Element Mismatch Shaping Algorithms in Incremental Delta-Sigma ADCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Using Negative-R Assisted Integrators in Wide-band Delta-Sigma Modulators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023

Delay Error Shaping in ΔΣ Modulators Using Time-Interleaved High Resolution Quantizers.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023

An Intrinsically Linear 13-Level Capacitive DAC for Delta Sigma Modulators.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, April, 2023

Bitwise ELD Compensation under Integrator Nonidealities in ΔΣ Modulators.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

A Chopped 6-bit 1.6 GS/s SAR ADC Utilizing Slow Decision Information in 22 nm FDSOI.

[BibT_eX]

[DOI]

Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

A 40 kS/sCalibration-Free Incremental △Σ ADC Achieving 104 dB DR and 105.7 dB SFDR.

[BibT_eX]

[DOI]

Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022

A Direct Digitizing Chopped Neural Recorder Using a Body-Induced Offset Based DC Servo Loop.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2022

A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta-Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

Maximizing the Inter-Stage Gain in CT 0-X MASH Delta-Sigma-Modulators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Bitwise ELD Compensation in Δ∑ Modulators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Complexity Reduced LUT-Based DAC Correction in Continuous-Time Delta-Sigma Modulators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

Minimizing Signal-Dependent Residue in CT Pipelined ADCs.

[BibT_eX]

[DOI]

Jonathan Ungethüm

John G. Kauffman

Maurits Ortmanns

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

Influence of Excess Loop Delay on the STF of Continuous-Time Delta-Sigma Modulators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

FIR Filter with Symmetric Non-Equal Coefficients for CT Delta-Sigma Modulators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Digital Resolution Requirements in 0-X MASH Delta-Sigma-Modulators.

[BibT_eX]

[DOI]

Jonathan Ungethüm

John G. Kauffman

Maurits Ortmanns

Proceedings of the 28th IEEE International Conference on Electronics, 2021

A Comparative Study of Noise Behavior in Single-Opamp Resonators in Delta-Sigma Modulators.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Conference on Electronics, 2021

A 0.9-V Calibration-Free 97dB-SFDR 2-MS/s Continuous Time Incremental Delta-Sigma ADC Utilizing Variable Bit Width Quantizer in 28nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020

FIR DACs in CT Incremental Delta-Sigma Modulators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A Comparative Study of ISI Errors in Different DAC Structures for CT Delta-Sigma Modulators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2018

A Multi-mode GSM to LTE100 ADC.

[BibT_eX]

[DOI]

Jens Sauerbrey

Jacinto San Pablo Garcia

Udo Schutz

Hasham Khushk

John G. Kauffman

Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2016

A 10 MHz Bandwidth, 70 dB SNDR Continuous Time Delta-Sigma Modulator With Digitally Improved Reconfigurable Blocker Rejection.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2016

2014

A 72 dB DR, CT ΔΣ Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2014

A 1.92-GS/s CT ΔΣ modulator with 70-db DR and 78-db SFDR in 15-MHz bandwidth.

[BibT_eX]

[DOI]

Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

2013

Integrator swing reduction in feedback compensated Sigma-Delta modulators.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A DAC cell with improved ISI and noise performance using native switching for multi-bit CT Delta Sigma modulators.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Low power quantizer design in CT Delta Sigma modulators.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Analysis and design of high speed/high linearity continuous time delta-sigma modulator.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012

PVT robust design of wideband CT delta sigma modulators including finite GBW compensation.

[BibT_eX]

[DOI]

John G. Kauffman

Timon Brückner

Maurits Ortmanns

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

A reconfigurable Continuous-Time ΔΣ-ADC using a digitally programmable gm-C array.

[BibT_eX]

[DOI]

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

A 72dB-DR ΔΣ CT modulator using digitally estimated auxiliary DAC linearization achieving 88fJ/conv in a 25MHz BW.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

An error estimation technique for lowpass and bandpass ΣΔ ADC feedback DACs using a residual test signal.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A power efficient MDAC design with correlated double sampling for a 2-step-flash ADC.

[BibT_eX]

[DOI]

Rudolf Ritter

John G. Kauffman

Maurits Ortmanns

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

A Correlation-Based Background Error Estimation Technique for Bandpass Delta-Sigma ADC DACs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2011

An 8.5 mW Continuous-Time ΔΣ Modulator With 25 MHz Bandwidth Using Digital Background DAC Linearization to Achieve 63.5 dB SNDR and 81 dB SFDR.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2011

An 8mW 50MS/s CT ΔΣ modulator with 81dB SFDR and digital background DAC linearization.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

John G. Kauffman

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