John F. McDonald

Affiliations:
  • Rensselaer Polytechnic Institute, Center for Integrated Electronics, Troy, NY, USA
  • Yale University, New Haven, CT, USA (PhD 1969)


According to our database1, John F. McDonald authored at least 66 papers between 1972 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
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PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2019
Automated Verification and Optimization of SFQ Superconducting Circuits.
IEEE Access, 2019

2015
High-Speed Reconfigurable Circuits for Multirate Systems in SiGe HBT Technology.
Proc. IEEE, 2015

140 Gb/s Serializer Using Clock Doublers in 90 nm SiGe Technology.
IEEE J. Solid State Circuits, 2015

Thermal Modeling of 3-D Stacked DRAM Over SiGe HBT BiCMOS CPU.
IEEE Access, 2015

2014
Design of High-Speed Register Files Using SiGe HBT BiCMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

Design of BiCMOS SRAMs for high-speed SiGe applications.
IET Circuits Devices Syst., 2014

2012
A Wide Band Locking Range Quarter-PhaseGenerator PLL Using 0.13um BiCMOS Technology.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

A three-dimensional DRAM using floating body cell in FDSOI devices.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
Carry Chains for Ultra High-Speed SiGe HBT Adders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Reconfigurable 40 GHz BiCMOS uniform delay crossbar switch for broadband and wide tuning range narrowband applications.
IET Circuits Devices Syst., 2011

2010
A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Correction to "A 40 GS/s Time Interleaved ADC Using SiGe BiCMOS Technology".
IEEE J. Solid State Circuits, 2010

A 40 Gs/s Time Interleaved ADC Using SiGe BiCMOS Technology.
IEEE J. Solid State Circuits, 2010

2009
Impact of Deep-Trench-Isolation-Sharing Techniques on Ultrahigh-Speed Digital Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks.
Proc. IEEE, 2009

Thermal analysis for a SiGe HBT 40 watt 32 GHz clock 3D memory processor chip stack using diamond heat spreader layers.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2007
A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2007

52 Gb/s 16: 1 transmitter in 0.13 μm SiGe BiCMOS technology.
IET Circuits Devices Syst., 2007

Silicon germanium programmable circuits for gigahertz applications.
IET Circuits Devices Syst., 2007

Amdahl's figure of merit, SiGe HBT BiCMOS, and 3D chip stacking.
Proceedings of the 25th International Conference on Computer Design, 2007

2006
Triple-rail MOS current mode logic for high-speed self-timed pipeline applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
SiGe HBT Microprocessor Core Test Vehicle.
Proc. IEEE, 2005

A 5-10GHz SiGe BiCMOS FPGA with new configurable logic block.
Microprocess. Microsystems, 2005

Multi-ghz Sige Bicmos Fpgas with New Architecture and Novel Power Management Techniques.
J. Circuits Syst. Comput., 2005

A 10 GHz 4: 1 MUX and 1: 4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC.
Integr., 2005

Predicting the Performance of a 3D Processor-Memory Chip Stack.
IEEE Des. Test Comput., 2005

12-23 GHz Ultra Wide Tuning Range Voltage-Controlled Ring Oscillator with Hybrid Control Schemes.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

A High Speed Reconfigurable Gate Array for Gigahertz Applications.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Multi-GHz SiGe design methodologies for reconfigurable computing.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

A 11 GHz FPGA with Test Applications.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004
The 10GHz 4: 1 MUX and 1: 4 DEMUX implemented via the gigahertz SiGe FPGA.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

The gigahertz FPGA: design consideration and applications.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

2003
A 5-20 GHz, low power FPGA implemented by SiGe HBT BiCMOS technology.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

3D direct vertical interconnect microprocessors test vehicle.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Gigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D Memory.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

A Novel Multi-Speed, Power Saving Architecture for SiGe HBT FPGA.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003

2002
A 32-word by 32-bit three-port bipolar register file implemented using a SiGe HBT BiCMOS technology.
IEEE J. Solid State Circuits, 2002

Gigahertz SiGe BiCMOS FPGAs with new architectures and novel power management schemes.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Fast SiGe HBT BiCMOS FPGAs with New Architecture and Power Saving Techniques.
Proceedings of the Field-Programmable Logic and Applications, 2002

Gigahertz FPGAs with New Power Saving Techniques and Decoding Logic.
Proceedings of the 4th NASA / DoD Workshop on Evolvable Hardware (EH 2002), 2002

2001
Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs.
Proceedings of the Field-Programmable Logic and Applications, 2001

2000
A 2-GHz clocked AlGaAs/GaAs HBT byte-slice datapath chip.
IEEE J. Solid State Circuits, 2000

1999
Optimal Differential Routing based on Finite State Machine Theory.
VLSI Design, 1999

Accurate high-speed performance prediction for full differential current-mode logic: the effect of dielectric anisotropy.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Reconfigurable FPGA's in the 1-20 GHz Band with HBT BiCMOS.
Proceedings of the 1st NASA / DoD Workshop on Evolvable Hardware (EH '99), 1999

1998
A very wide bandwidth digital VCO using quadrature frequency multiplication and division implemented in AlGaAs/GaAs HBT's.
IEEE Trans. Very Large Scale Integr. Syst., 1998

1997
Design of a 32 b monolithic microprocessor based on GaAs HMESFET technology.
IEEE Trans. Very Large Scale Integr. Syst., 1997

1996
Chip Pad Migration is a Key Component to High Performance MCM Design.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

1994
Differential Routing of MCMs - CIF: The Ideal Bifurcation Medium.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Wiring pitch integrates MCM design domains.
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

Design of a package for a high-speed processor made with yield-limited technology.
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

1993
MCM: The High-Performance Electronic Packaging Technology.
Computer, 1993

1987
A video rate architecture for a fully recursive two-dimensional filter.
Proceedings of the IEEE International Conference on Acoustics, 1987

Benchmark Runs of the Subscripted D-Algorithm with Observation Path Mergers on the Brglez-Fujiwara Circuits.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1986
Use of the subscripted DALG in submodule testing with applications in cellular arrays.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1983
Measured performance of a programmed implementation of the subscripted D-Algorithm.
Proceedings of the 20th Design Automation Conference, 1983

1982
Homomorphic signal dereverberation for a phased array imaging system.
Proceedings of the IEEE International Conference on Acoustics, 1982

1979
Minimax optimization of two-dimensional focused nonuniformly spaced arrays.
Proceedings of the IEEE International Conference on Acoustics, 1979

1976
Second-Order Statistical Moments of a Surface Scatter Channel with Multiple Wave Direction and Dispersion.
IEEE Trans. Commun., 1976

1975
Experimental Measurement of the Second-Order Interfrequency Correlation Function of the Random Surface Scatter Channel.
IEEE Trans. Commun., 1975

1974
Fresnel-Corrected Second-Order Interfrequency Correlations for a Surface-Scatter Channel.
IEEE Trans. Commun., 1974

Controller for a flexible disk.
Proceedings of the American Federation of Information Processing Societies: 1974 National Computer Conference, 1974

1973
Three ECL designs for microprogrammable Writable Control Stores.
Proceedings of the Conference record of the 6th annual workshop on Microprogramming, 1973

1972
ISPMET: a study in automatic emulator generation.
Proceedings of the Conference record of the 5th annual workshop on Microprogramming, 1972


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