John F. Brown III

According to our database, John F. Brown III authored at least 6 papers between 1984 and 2008.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2008

TILE64 - Processor: A 64-Core SoC with Mesh Interconnect.

Shane Bell, Bruce Edwards, John Amann, Rich Conlin, Kevin Joyce, Vince Leung, John MacKay, Mike Reif, Liewei Bao, John F. Brown III, Matthew Mattina, Chyi-Chang Miao, Carl Ramey, David Wentzlaff, Walker Anderson, Ethan Berger, Nat Fairbanks, Durlov Khan, Froilan Montenegro, Jay Stickney, John Zook

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

On-Chip Interconnection Architecture of the Tile Processor.

David Wentzlaff, Patrick Griffin, Henry Hoffmann, Liewei Bao, Bruce Edwards, Carl Ramey, Matthew Mattina, Chyi-Chang Miao, John F. Brown III, Anant Agarwal

IEEE Micro, 2007

1992

The NVAX and NVAX+ High-Performance VAX Microprocessor.

G. Michael Uhler, Debra Bernstein, Larry L. Biro, John F. Brown III, John H. Edmondson, Jeffrey D. Pickholtz, Rebecca L. Stamm

Digit. Tech. J., 1992

NVAX and NVAX + Single-Chip CMOS VAX Microprocessors.

Debra Bernstein, John F. Brown III, Rebecca L. Stamm, G. Michael Uhler

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

1984

Design verification of a VLSI VAX microcomputer.

Sridhar Samudrala, Charles Lo, John F. Brown III, Richard E. Calcagni

Proceedings of the 17th annual workshop on Microprogramming, 1984

A chip set microarchitecture for a high-performance VAX implementation.

John F. Brown III, Richard L. Sites

Proceedings of the 17th annual workshop on Microprogramming, 1984