John Charles Wright
Orcid: 0000-0001-6363-0462
According to our database1,
John Charles Wright
authored at least 11 papers
between 2019 and 2022.
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Bibliography
2022
IEEE J. Solid State Circuits, 2022
A Ring-Oscillator Sub-Sampling PLL With Hybrid Loop Using Generator-Based Design Flow.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A 16mm<sup>2</sup> 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET.
Proceedings of the 47th ESSCIRC 2021, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs.
IEEE Micro, 2020
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
Gemmini: An Agile Systolic Array Generator Enabling Systematic Evaluations of Deep-Learning Architectures.
CoRR, 2019