John C. Liobe

Orcid: 0000-0001-7268-5991

According to our database1, John C. Liobe authored at least 13 papers between 2003 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Applying smart devices for gathering real-time feedback from students.
Comput. Appl. Eng. Educ., 2021

2014
Indirect-Feedback Sigma-Delta Image Sensors: Theory, Modeling and Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

2013
Implementing OCEAN scripts in RF circuit design.
Proceedings of the 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, 2013

Noise model of indirect-feedback sigma-delta image sensors.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
pbCAM: Probabilistically-banked Content Addressable Memory.
Proceedings of the IEEE 25th International SOC Conference, 2012

2008
Experimental Analysis of Substrate Noise Effect on PLL Performance.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

A Novel Application of FM-ADC Toward the Self-Calibration of Phase-Locked Loops.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

2007
Novel Process and Temperature-Stable, IDD Sensor for the BIST Design of Embedded Digital, Analog, and Mixed-Signal Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Process and Temperature Calibration of PLLs with BiST Capabilities.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Novel Process and Temperature-Stable BICS for Embedded Analog and Mixed-Signal Test.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

2006
Process tolerant calibration circuit for PLL applications with BIST.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
A New Test Methodology For DNL Error In Flash ADC's.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2003
Deep-Submicron CMOS Design Methodology for High-Performance Low-Power Analog-to-Digital Converters.
Proceedings of the IFIP VLSI-SoC 2003, 2003


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