John C. Eble

According to our database1, John C. Eble authored at least 12 papers between 1999 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2015
A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology.
IEEE J. Solid State Circuits, 2015

2014
A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface.
IEEE J. Solid State Circuits, 2014

A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems.
IEEE J. Solid State Circuits, 2014

A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering.
Proceedings of the Symposium on VLSI Circuits, 2014

2013
A 6.4Gb/s near-ground single-ended transceiver for dual-rank DIMM memory interface systems.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

A 2.3-4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-on.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques.
IEEE J. Solid State Circuits, 2011

Power-efficient I/O design considerations for high-bandwidth applications.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
A 32mW 7.4Gb/s protocol-agile source-series-terminated transmitter in 45nm CMOS SOI.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2000
Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance.
IEEE J. Solid State Circuits, 2000

1999
A physical alpha-power law MOSFET model.
IEEE J. Solid State Circuits, 1999


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