John Barth

According to our database, John Barth authored at least 16 papers between 1995 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2012

Isolated Preset Architecture for a 32nm SOI embedded DRAM macro.

John Barth, Don Plass, Adis Vehabovic, Rajiv V. Joshi, Rouwaida Kanj, Steven Burns, Todd Weaver

Proceedings of the Symposium on VLSI Circuits, 2012

Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond.

Balaji Jayaraman, Sneha Gupta, Yanli Zhang, Puneet Goyal, Herbert Ho, Rishikesh Krishnan, Sunfei Fang, Sungjae Lee, Douglas Daley, Kevin McStay, Bernhard Wunder, John Barth, Sadanand Deshpande, Paul C. Parries, Rajeev Malik, Paul D. Agnello, Scott R. Stiffler, Subramanian S. Iyer

Proceedings of the IEEE International Conference on IC Design & Technology, 2012

2011

A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache.

John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, Toshiaki Kirihata, William R. Reohr, Kavita Nair, Nianzheng Cao

IEEE J. Solid State Circuits, 2011

Three Dimensional integration - Considerations for memory applications.

Subramanian S. Iyer, Toshiaki Kirihata, John E. Barth Jr.

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010

A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache.

John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, William R. Reohr, Kavita Nair, Nianzheng Cao

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.

Peter J. Klim, John Barth, William R. Reohr, David Dick, Gregory Fredeman, Gary Koch, Hien M. Le, Aditya Khargonekar, Pamela Wilcox, John Golz, Jente B. Kuang, Abraham Mathews, Jethro C. Law, Trong Luong, Hung C. Ngo, Ryan Freese, Hillery C. Hunter, Erik Nelson, Paul C. Parries, Toshiaki Kirihata, Subramanian S. Iyer

IEEE J. Solid State Circuits, 2009

2008

A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier.

John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer

IEEE J. Solid State Circuits, 2008

An on-chip dual supply charge pump system for 45nm PD SOI eDRAM.

Jente B. Kuang, Abraham Mathews, John Barth, Fadi H. Gebara, Tuyet Nguyen, Jeremy D. Schaub, Kevin J. Nowka, Gary D. Carpenter, Don Plass, Erik Nelson, Ivan Vo, William R. Reohr, Toshiaki Kirihata

Proceedings of the ESSCIRC 2008, 2008

2007

A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier.

John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005

A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining.

John E. Barth Jr., Darren Anand, Steve Burns, Jeffrey H. Dreibelbis, John A. Fifield, Kevin W. Gorman, Michael R. Nelms, Erik Nelson, Adrian Paparelli, Gary Pomichter, Dale E. Pontius, Stephen Sliva

IEEE J. Solid State Circuits, 2005

Embedded DRAM: Technology platform for the Blue Gene/L chip.

Subramanian S. Iyer, John E. Barth Jr., Paul C. Parries, James P. Norum, James P. Rice, Lyndon R. Logan, Dennis Hoyniak

IBM J. Res. Dev., 2005

2003

A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface.

Harold Pilo, Darren Anand, John Barth, Steve Burns, Phil Corson, Jim Covino, Steve Lamphier

IEEE J. Solid State Circuits, 2003

2002

Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering.

John E. Barth Jr., Jeffrey H. Dreibelbis, Eric A. Nelson, Darren Anand, Gary Pomichter, Peter Jakobsen, Michael R. Nelms, Jeffrey Leach, George M. Belansek

IBM J. Res. Dev., 2002

2001

Embedded DRAM built in self test and methodology for test insertion.

Peter Jakobsen, Jeffrey H. Dreibelbis, Gary Pomichter, Darren Anand, John Barth, Michael R. Nelms, Jeffrey Leach, George M. Belansek

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

1998

Processor-based built-in self-test for embedded DRAM.

Jeffrey H. Dreibelbis, John Barth, Howard L. Kalter, Rex Kho

IEEE J. Solid State Circuits, 1998

1995

Multipurpose DRAM architecture for optimal power, performance, and product flexibility.

Wayne F. Ellis, John E. Barth Jr., Sri Divakaruni, Jeffrey H. Dreibelbis, Anatol Furman, Erik L. Hedberg, Hsing-San Lee, Thomas M. Maffitt, Christopher P. Miller, Charles H. Stapper, Howard L. Kalter

IBM J. Res. Dev., 1995