John Bainbridge

According to our database1, John Bainbridge authored at least 11 papers between 1990 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2011
SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip.
ACM J. Emerg. Technol. Comput. Syst., 2011

2008
An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

2007
Asynchronous on-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral Bus.
Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 2007

2005
Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Future Trends in SoC Interconnect.
Proceedings of the 2005 International Symposium on System-on-Chip, 2005

2004
Sparse distributed memory using <i>N</i>-of-<i>M</i> codes.
Neural Networks, 2004

Adding Testability to an Asynchronous Interconnect for GALS SoC.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2002
Chain: A Delay-Insensitive Chip Area Interconnect.
IEEE Micro, 2002

1994
Defining Testability Metrics Axiomatically.
Softw. Test. Verification Reliab., 1994

1992
A Heuristic Method for Generating Large Random Expressions.
Inf. Process. Lett., 1992

1990
Obtaining Structural Metrics of Z Specifications for Systems Development.
Proceedings of the Z User Workshop, 1990


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