John A. Nestor

According to our database, John A. Nestor authored at least 22 papers between 1983 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Experiences with Remote Teaching an Embedded Systems Course.

John A. Nestor

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2017

From microelectronics to making: Incorporating microelectronics in a first-year engineering course.

John A. Nestor

Proceedings of the 2017 IEEE International Conference on Microelectronic Systems Education, 2017

2011

HDL coding guidelines for student projects.

John A. Nestor

Proceedings of the 2011 IEEE International Conference on Microelectronic Systems Education, 2011

An undergraduate embedded systems project.

John F. Greco, John A. Nestor

Proceedings of the 2011 IEEE International Conference on Microelectronic Systems Education, 2011

2010

VCache: visualization applet for processor caches.

Berkin Ilbeyi, John A. Nestor

Proceedings of the 15th Annual SIGCSE Conference on Innovation and Technology in Computer Science Education, 2010

2009

An FPGA-based wireless network capstone project.

John A. Nestor, Chris Nadovich

Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2009

2008

Experience With the CADAPPLETS Project.

John A. Nestor

IEEE Trans. Educ., 2008

2007

L4: An FPGA-Based Accelerator for Detailed Maze Routing.

John A. Nestor, Jeremy Lavine

Proceedings of the FPL 2007, 2007

2005

L3: An FPGA-based multilayer maze routing accelerator.

John A. Nestor

Microprocess. Microsystems, 2005

Teaching Computer Organization with HDLs: An Incremental Approach.

John A. Nestor

Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005

2003

Integrating Digital, Analog, and Mixed-Signal Design in an Undergraduate ECE Curriculum.

John A. Nestor, David A. Rich

Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

FPGA Implementation of a Maze Routing Accelerator.

John A. Nestor

Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002

A new look at hardware maze routing.

John A. Nestor

Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

2001

Web-Based Visualization Tools for Teaching VLSI CAD Algorithms.

John A. Nestor

Proceedings of the 2001 International Conference on Microelectronics Systems Education, 2001

1993

Visual register-transfer description of VLSI microarchitectures.

John A. Nestor

IEEE Trans. Very Large Scale Integr. Syst., 1993

SALSA: a new approach to scheduling with timing constraints.

John A. Nestor, Ganesh Krishnamoorthy

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

SALSE II: A Fast Transformational Scheduler for High-level Synthesis.

Michael R. Rhinehart, John A. Nestor

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1992

Data Path Allocation using an Extended Binding Model.

Ganesh Krishnamoorthy, John A. Nestor

Proceedings of the 29th Design Automation Conference, 1992

1989

MIES: a microarchitecture design tool.

John A. Nestor, Bassel Soudan, Zubair Mayet

Proceedings of the 22nd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1989

1988

The System Architect's Workbench.

Donald E. Thomas, Elizabeth M. Dirkes, Robert A. Walker, Jayanth V. Rajan, John A. Nestor, Robert L. Blackburn

Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1984

DIF: A framework for VLSI multi-level representation.

David P. LaPotin, Sani R. Nassif, Jayanth V. Rajan, Michael L. Bushnell, John A. Nestor

Integr., 1984

1983

Defining and Implementing a Multilevel Design Representation with Simulation Applications.

Donald E. Thomas, John A. Nestor

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983