John A. Kalomiros

Orcid: 0000-0002-1790-0975

Affiliations:
  • Technological Educational Institute of Serres, Greece


According to our database1, John A. Kalomiros authored at least 30 papers between 2006 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
A Hardware Accelerator for the Semi-Global Matching Stereo Algorithm: An Efficient Implementation for the Stratix V and Zynq UltraScale+ FPGA Technology.
ACM Trans. Reconfigurable Technol. Syst., March, 2024

2023
Implementation of a Sequence-to-Sequence Stacked Sparse Long Short-Term Memory Autoencoder for Anomaly Detection on Multivariate Timeseries Data of Industrial Blower Ball Bearing Units.
Sensors, July, 2023

A Testbench for Stereo-Processing Acceleration Based on PYNQ and the StereoPi.
Proceedings of the 12th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, 2023

2021
A Workflow for Designing Video Processing Pipelines with PYNQ.
Proceedings of the 2021 11th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS), 2021

The Robin Soft-Core: A Paradigm for Studying VHDL and Computer Architecture.
Proceedings of the 2021 11th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS), 2021

2020
EUROPA: A Case Study for Teaching Sensors, Data Acquisition and Robotics via a ROS-Based Educational Robot.
Sensors, 2020

2019
EUROPA - A ROS-based Open Platform for Educational Robotics.
Proceedings of the 10th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, 2019

Chaotic Map Synchronization by Common-Mode Truncation Pulses for Secure Communications.
Proceedings of the 10th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, 2019

2018
FPGA-based architecture of a real-time SIFT matcher and RANSAC algorithm for robotic vision applications.
Multim. Tools Appl., 2018

2017
FPGA accelerator for real-time SIFT matching with RANSAC support.
Microprocess. Microsystems, 2017

Implementation of a V/ƒ motor speed controller using a matrix converter and fuzzy asymmetrical PWM.
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

Intelligent speed controller for single-phase induction motors using fuzzy APWM.
Proceedings of the 9th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, 2017

A complete processor for SIFT feature matching in video sequences.
Proceedings of the 9th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, 2017

2016
Fully pipelined FPGA-based architecture for real-time SIFT extraction.
Microprocess. Microsystems, 2016

2015
Design details of a low Cost and High Performance robotic Vision Architecture.
Int. J. Comput., 2015

An embedded fuzzy controller for the soft-starting of low-voltage induction motors.
Proceedings of the IEEE 8th International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, 2015

Intrinsic evolution of digital circuits based on a reconfigurable hyper-structure.
Proceedings of the IEEE EUROCON 2015, 2015

2013
Development of an odor-discriminating sensor-array for the Detection of the aroma of ascomycete tuber.
Proceedings of the IEEE 7th International Conference on Intelligent Data Acquisition and Advanced Computing Systems, 2013

Optimization of a Scale-Invariant Feature detector using scale-space scans.
Proceedings of the IEEE 7th International Conference on Intelligent Data Acquisition and Advanced Computing Systems, 2013

2012
Dense disparity features for fast stereo vision.
J. Electronic Imaging, 2012

Acceleration of Image Processing Algorithms Using Minimal Resources of Custom Reconfigurable Hardware.
Proceedings of the 16th Panhellenic Conference on Informatics, PCI 2012, 2012

2011
Design and hardware implementation of a stereo-matching system based on dynamic programming.
Microprocess. Microsystems, 2011

2010
Robotic Mapping and Localization with Real-Time Dense Stereo on Reconfigurable Hardware.
Int. J. Reconfigurable Comput., 2010

2009
Comparative Study of Local SAD and Dynamic Programming for Stereo Processing Using Dedicated Hardware.
EURASIP J. Adv. Signal Process., 2009

A Reconfigurable Architecture for Stereo-Assisted Detection of Point-Features for Robot Mapping.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

2008
Design and evaluation of a hardware/software FPGA-based system for fast image processing.
Microprocess. Microsystems, 2008

Hardware implementation of a stereo co-processor in a medium-scale field programmable gate array.
IET Comput. Digit. Tech., 2008

2007
Optimization of Al/a-SiC: H optical sensor device by means of thermal annealing.
Microelectron. J., 2007

2006
Optimization of the electrical properties of Al/a-SiC: H Schottky diodes by means of thermal annealing of a-SiC: H thin films.
Microelectron. J., 2006

Real Time Data Acquisition System for the ECP-EPP Parallel Port based on PIC16F877 Microcontroller.
Int. J. Comput., 2006


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