John A. Fifield

According to our database1, John A. Fifield authored at least 5 papers between 1990 and 2018.

Collaborative distances:

Timeline

1990
1995
2000
2005
2010
2015
0
1
2
1
1
1
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Other 

Links

On csauthors.net:

Bibliography

2018
14NM FinFET 1.5MB Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Dynamic Adaptive Programming.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2010
A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2007
A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2005
A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining.
IEEE J. Solid State Circuits, 2005

1990
A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC.
IEEE J. Solid State Circuits, October, 1990


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