John A. Chandy

Orcid: 0000-0003-3449-3205

Affiliations:
  • University of Connecticut, USA


According to our database1, John A. Chandy authored at least 89 papers between 1993 and 2023.

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Bibliography

2023
Translation of AADL model to security attack tree (TAMSAT) to SMART evaluation of monetary security risk.
Inf. Secur. J. A Glob. Perspect., July, 2023

2022
A framework for evaluating security risk in system design.
Discov. Internet Things, 2022

Extracting Vulnerabilities from GitHub Commits.
Proceedings of the IEEE International Conference on Software Analysis, 2022

Cache Locking and Encryption to Prevent Memory Snooping in Embedded Systems.
Proceedings of the IEEE Conference on Dependable and Secure Computing, 2022

2020
SMART: security model adversarial risk-based tool for systems security design evaluation.
J. Cybersecur., 2020

Exploring the Coverage of Existing Hardware Vulnerabilities in Community Standards.
Proceedings of the Silicon Valley Cybersecurity Conference - First Conference, 2020

A Trace-Based Study of SMB Network File System Workloads in an Academic Enterprise.
Proceedings of the 2020 International Symposium on Performance Evaluation of Computer and Telecommunication Systems, 2020

Embedded Systems Authentication and Encryption Using Strong PUF Modeling.
Proceedings of the 2020 IEEE International Conference on Consumer Electronics (ICCE), 2020

Bit<sup>2</sup>RNG: Leveraging Bad-page Initialized Table with Bit-error Insertion for True Random Number Generation in Commodity Flash Memory.
Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust, 2020

FLASH: FPGA Locality-Aware Sensitive Hash for Nearest Neighbor Search and Clustering Application.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

2019
Eight-bit ADC using non-volatile flash memory.
IET Circuits Devices Syst., 2019

Key Generation for Hardware Obfuscation Using Strong PUFs.
Cryptogr., 2019

HOTMeTaL: Hardware Optimization Tool for Memory Table and Logic Conversion.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018
DVFT: A Lightweight Solution for Power-Supply Noise-Based TRNG Using Dynamic Voltage Feedback Tuning System.
IEEE Trans. Very Large Scale Integr. Syst., 2018

P2M-based security model: security enhancement using combined PUF and PRNG models for authenticating consumer electronic devices.
IET Comput. Digit. Tech., 2018

An Overview of DRAM-Based Security Primitives.
Cryptogr., 2018

Phase Calibrated Ring Oscillator PUF Design and Application.
Comput., 2018

Low-cost authentication paradigm for consumer electronics within the internet of wearable fitness tracking applications.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

Error Tolerant ASCA on FPGA.
Proceedings of the Cloud Computing and Security - 4th International Conference, 2018

An Adversarial Risk-based Approach for Network Architecture Security Modeling and Design.
Proceedings of the 2018 International Conference on Cyber Security and Protection of Digital Services, 2018

2017
DRAM-Based Intrinsic Physically Unclonable Functions for System-Level Security and Authentication.
IEEE Trans. Very Large Scale Integr. Syst., 2017

PUF-Based Fuzzy Authentication Without Error Correcting Codes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Algebraic Side-Channel Attack on Twofish.
J. Internet Serv. Inf. Secur., 2017

A Study of Power Supply Variation as a Source of Random Noise.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

A design flow with integrated verification of requirements and faults in safety-critical systems.
Proceedings of the 12th System of Systems Engineering Conference, 2017

DRNG: DRAM-based random number generation using its startup value behavior.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Investigation of DRAM PUFs reliability under device accelerated aging effects.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Phase calibrated ring oscillator PUF design and implementation on FPGAs.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Influence of Error on Hamming Weights for ASCA.
Proceedings of the Information Security and Cryptology - 13th International Conference, 2017

Proposing a modeling framework for minimizing security vulnerabilities in IoT systems in the healthcare domain.
Proceedings of the 2017 IEEE EMBS International Conference on Biomedical & Health Informatics, 2017

2016
Adding data analytics capabilities to scaled-out object store.
J. Syst. Softw., 2016

A Survey on Chip to System Reverse Engineering.
ACM J. Emerg. Technol. Comput. Syst., 2016

Exploiting user metadata for energy-aware node allocation in a cloud storage system.
J. Comput. Syst. Sci., 2016

Robust hardware true random number generators using DRAM remanence effects.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

2015
Unipolar Logic Gates Based on Spatial Wave-Function Switched FETs.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Active storage networks: Using embedded computation in the network switch for cluster data processing.
Future Gener. Comput. Syst., 2015

Leveraging checkpoint/restore to optimize utilization of cloud compute resources.
Proceedings of the 40th IEEE Local Computer Networks Conference Workshops, 2015

A Novel Way to Authenticate Untrusted Integrated Circuits.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

DRAM based Intrinsic Physical Unclonable Functions for System Level Security.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014
Implementation of Six Bit ADC and DAC Using Quantum Dot Gate Non-Volatile Memory.
J. Signal Process. Syst., 2014

Using an Object-Based Active Storage Framework to Improve Parallel Storage Systems.
Proceedings of the 43rd International Conference on Parallel Processing Workshops, 2014

Creating a programmable object storage stack.
Proceedings of the PFSW'14, 2014

2013
Design of Ternary Logic Combinational Circuits Based on Quantum Dot Gate FETs.
IEEE Trans. Very Large Scale Integr. Syst., 2013

An object interface storage node for clustered file systems.
Proceedings of the 2013 IEEE International Conference on Cluster Computing, 2013

Optimizations on the Parallel Virtual File System implementation integrated with Object-Based Storage Devices.
Proceedings of the 2013 IEEE International Conference on Cluster Computing, 2013

2012
A Case for Optimistic Coordination in HPC Storage Systems.
Proceedings of the 2012 SC Companion: High Performance Computing, 2012

An active storage framework for object storage devices.
Proceedings of the IEEE 28th Symposium on Mass Storage Systems and Technologies, 2012

Techniques for an energy aware parallel file system.
Proceedings of the 2012 International Green Computing Conference, 2012

2011
2-Dilated flattened butterfly: A nonblocking switching topology for high-radix networks.
Comput. Commun., 2011

Active Storage Networks for Accelerating K-Means Data Clustering.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010
ATTEST: ATTributes-based Extendable STorage.
J. Syst. Softw., 2010

Parallel Data Sort Using Networked FPGAs.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Extendable storage framework for reliable clustered storage systems.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

2-dilated flattened butterfly: A nonblocking switching network.
Proceedings of the 11th IEEE International Conference on High Performance Switching and Routing, 2010

2009
An Analysis of Parallel Programming Techniques for Data Intensive Computation.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2009

An analysis of resource costs in a public computing grid.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

2008
RAID0.5: design and implementation of a low cost disk array data protection method.
J. Supercomput., 2008

FPGA based string matching for network processing applications.
Microprocess. Microsystems, 2008

Multiple Valued Logic Using 3-State Quantum Dot Gate FETs.
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008

Active storage using object-based devices.
Proceedings of the 2008 IEEE International Conference on Cluster Computing, 29 September, 2008

2007
Reliability tradeoffs in personal storage systems.
ACM SIGOPS Oper. Syst. Rev., 2007

Dual actuator logging disk architecture and modeling.
J. Syst. Archit., 2007

2006
A CAM-based keyword match processor architecture.
Microelectron. J., 2006

RAID0.5: Active Data Replication for Low Cost Disk Array Data Protection.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications & Conference on Real-Time Computing Systems and Applications, 2006

A Generic Lookup Cache Architecture for Network Processing Applications.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

Storage Allocation in Unreliable Peer-to-Peer Systems.
Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN 2006), 2006

2005
A Quorum Based Content Delivery Architecture.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

A Signature Match Processor Architecture for Network Intrusion Detection.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

2004
Parity Redundancy Strategies in a Large Scale Distributed Storage System.
Proceedings of the 21st IEEE Conference on Mass Storage Systems and Technologies / 12th NASA Goddard Conference on Mass Storage Systems and Technologies, 2004

A keyword match processor architecture using content addressable memory.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

FPGA Based Network Intrusion Detection using Content Addressable Memories.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

2003
Data Integrity in a Distributed Storage System.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

A Scalable Architecture for Clustered Network Attached Storage.
Proceedings of the 20th IEEE/11th NASA Goddard Conference on Mass Storage Systems and Technologies, 2003

1999
A Parallel Circuit-Partitioned Algorithm for Timing-Driven Standard Cell Placement.
J. Parallel Distributed Comput., 1999

1998
WADE: a Web-based automated parallel CAD environment.
Proceedings of the 5th International Conference On High Performance Computing, 1998

1997
An evaluation of parallel simulated annealing strategies with application to standard cell placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Parallel Global Routing Algorithms for Standard Cells.
Proceedings of the 11th International Parallel Processing Symposium (IPPS '97), 1997

Performance Evaluation of Message-Driven Parallel VLSI CAD Applications on General Purpose Multiprocessors.
Proceedings of the 11th international conference on Supercomputing, 1997

A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996
Parallel simulated annealing strategies for VLSI cell placement.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Distributed Object Oriented Data Structures and Algorithms for VLSI CAD.
Proceedings of the Parallel Algorithms for Irregularly Structured Problems, 1996

1995
The Paradigm Compiler for Distributed-Memory Multicomputers.
Computer, 1995

Parallel algorithms for logic synthesis using the MIS approach.
Proceedings of IPPS '95, 1995

1994
A library-based approach to portable, parallel, object-oriented programming: interface, implementation, and application.
Proceedings of the Proceedings Supercomputing '94, 1994

ProperPLACE: A Portable Parallel Algorithm for Standard Cell Placement.
Proceedings of the 8th International Symposium on Parallel Processing, 1994

Communication Optimizations Used in the PARADIGM Compiler for Distributed Memory Multicomputers.
Proceedings of the 1994 International Conference on Parallel Processing, 1994

1993
Design and Evaluation of Gracefully Degradable Disk Arrays.
J. Parallel Distributed Comput., 1993

Reliability Evalutaion of Disk Array Architectures.
Proceedings of the 1993 International Conference on Parallel Processing, 1993

Failure Evaluation of Disk Array Organizations.
Proceedings of the 13th International Conference on Distributed Computing Systems, 1993


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