Johannes Schreiner

According to our database1, Johannes Schreiner authored at least 8 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Model-based Generation of Highly Configurable RTL Designs.
PhD thesis, 2024

The Argument for Meta-Modeling-Based Approaches to Hardware Generation Languages.
CoRR, 2024

2023
Generator IP-reuse and Automated Infrastructure Generation for Model-based Full-Chip Generation.
Proceedings of the Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2023

2017
Metamodeling and Code Generation in the Hardware/Software Interface Domain.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

Python based framework for HDSLs with an underlying formal semantics: (Invited paper).
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016
Digital Hardware Design Based on Metamodels and Model Transformations.
Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016

Introducing Model-of-Things (MoT) and Model-of-Design (MoD) for simpler and more efficient hardware generators.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Design centric modeling of digital hardware.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016


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