Johann Laurent
According to our database1,
Johann Laurent
authored at least 27 papers
between 2002 and 2023.
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Bibliography
2023
IEEE Trans Autom. Sci. Eng., October, 2023
2021
Design and Comparison of Reward Functions in Reinforcement Learning for Energy Management of Sensor Nodes.
CoRR, 2021
2020
Comparison of Market-based and DQN methods for Multi-Robot processing Task Allocation (MRpTA).
Proceedings of the Fourth IEEE International Conference on Robotic Computing, 2020
2019
J. Low Power Electron., 2019
2017
J. Low Power Electron., 2017
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017
2016
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016
2014
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014
2012
2011
PerTurbo: A New Classification Algorithm Based on the Spectrum Perturbations of the Laplace-Beltrami Operator.
Proceedings of the Machine Learning and Knowledge Discovery in Databases, 2011
2010
Spatial Switching Data Coding Technique Analysis and Improvements for Interconnect Power Consumption Optimization.
J. Low Power Electron., 2010
2009
Energy and Power Consumption Estimation for Embedded Applications and Operating Systems.
J. Low Power Electron., 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Model Driven High-Level Power Estimation of Embedded Operating Systems Communication Services.
Proceedings of the International Conference on Embedded Software and Systems, 2009
2008
Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
Proceedings of the Forum on specification and Design Languages, 2008
Proceedings of the Languages for Embedded Systems and their Applications, 2008
2007
Tech. Sci. Informatiques, 2007
2005
SoftExplorer: Estimating and Optimizing the Power and Energy Consumption of a C Program for DSP Applications.
EURASIP J. Adv. Signal Process., 2005
Power/Energy Estimation in SoCs by Multi-Level Parametric Modeling.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005
2004
SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level.
Proceedings of the Integrated Circuit and System Design, 2004
Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors.
Proceedings of the 2004 Design, 2004
2003
2002
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002
Power Estimation of a C Algorithm Based on the Functional-Level Power Analysis of a Digital Signal Processor.
Proceedings of the High Performance Computing, 4th International Symposium, 2002