Johann Knechtel

IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

NiLoPher: Breaking a Modern SAT-Hardened Logic-Locking Scheme via Power Analysis Attack.

[BibT_eX]

[DOI]

Debdeep Mukhopadhyay

Ramesh Karri

IACR Cryptol. ePrint Arch., 2024

Trojan Insertion versus Layout Defenses for Modern ICs: Red-versus-Blue Teaming in a Competitive Community Effort.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2024

ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search.

[BibT_eX]

[DOI]

Jitendra Bhandari

Animesh Basak Chowdhury

CoRR, 2024

LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines.

[BibT_eX]

[DOI]

CoRR, 2024

TroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans.

[BibT_eX]

[DOI]

CoRR, 2024

Lightweight Masking Against Static Power Side-Channel Attacks.

[BibT_eX]

[DOI]

Jitendra Bhandari

CoRR, 2024

MCS-NTT: Multi-Chip System Design for NTT Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024

The Impact of Logic Synthesis and Technology Mapping on Logic Locking Security.

[BibT_eX]

[DOI]

Lilas Alrahis

Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024

LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Code-Based Cryptography for Confidential Inference on FPGAs: An End-to-End Methodology.

[BibT_eX]

[DOI]

Rupesh Raj Karn

Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

Obfuscation of FSMs for Secure Outsourcing of Neural Network Inference onto FPGAs.

[BibT_eX]

[DOI]

Rupesh Raj Karn

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023

VIGILANT: Vulnerability Detection Tool Against Fault-Injection Attacks for Locking Techniques.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

Titan: Security Analysis of Large-Scale Hardware Obfuscation Using Graph Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Forensics Secur., 2023

DEFending Integrated Circuit Layouts.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2023

UN-SPLIT: Attacking Split Manufacturing Using Link Prediction in Graph Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2023

Security Closure of IC Layouts Against Hardware Trojans.

[BibT_eX]

[DOI]

Proceedings of the 2023 International Symposium on Physical Design, 2023

X-Volt: Joint Tuning of Driver Strengths and Supply Voltages Against Power Side-Channel Attacks.

[BibT_eX]

[DOI]

Saideep Sreekumar

Mohammed Ashraf

Proceedings of the 2023 International Symposium on Physical Design, 2023

Benchmarking Advanced Security Closure of Physical Layouts: ISPD 2023 Contest.

[BibT_eX]

[DOI]

Proceedings of the 2023 International Symposium on Physical Design, 2023

TrojanSAINT: Gate-Level Netlist Sampling-Based Inductive Learning for Hardware Trojan Detection.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning.

[BibT_eX]

[DOI]

Animesh Basak Chowdhury

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs.

[BibT_eX]

[DOI]

Lilas Alrahis

Santosh Kumar Vishvakarma

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

Opening the Doors to Dynamic Camouflaging: Harnessing the Power of Polymorphic Devices.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

A Novel Attack Mode on Advanced Technology Nodes Exploiting Transistor Self-Heating.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Concerted Wire Lifting: Enabling Secure and Cost-Effective Split Manufacturing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Design-time exploration of voltage switching against power analysis attacks in 14 nm FinFET technology.

[BibT_eX]

[DOI]

Integr., 2022

IsoLock: Thwarting Link-Prediction Attacks on Routing Obfuscation by Graph Isomorphism.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2022

SuperVAULT: Superparamagnetic Volatile Auxiliary Tamper-Proof Storage.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2022

A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL.

[BibT_eX]

[DOI]

Cryptogr., 2022

Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2022

SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture.

[BibT_eX]

[DOI]

Akash Kumar

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Benchmarking Security Closure of Physical Layouts: ISPD 2022 Contest.

[BibT_eX]

[DOI]

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

2021

UNSAIL: Thwarting Oracle-Less Machine Learning Attacks on Logic Locking.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Forensics Secur., 2021

A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2021

Deep Learning Analysis for Split-Manufactured Layouts With Routing Perturbation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Interposer-Based Root of Trust.

[BibT_eX]

[DOI]

CoRR, 2021

Hardware Security for and beyond CMOS Technology.

[BibT_eX]

[DOI]

Proceedings of the ISPD '21: International Symposium on Physical Design, 2021

Toward Security Closure in the Face of Reliability Effects ICCAD Special Session Paper.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Security Closure of Physical Layouts ICCAD Special Session Paper.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

2020

Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2020

Power Side-Channel Attacks in Negative Capacitance Transistor.

[BibT_eX]

[DOI]

IEEE Micro, 2020

Power Side-Channel Attacks in Negative Capacitance Transistor (NCFET).

[BibT_eX]

[DOI]

CoRR, 2020

SMART: A Secure Magnetoelectric AntifeRromagnet-Based Tamper-Proof Non-Volatile Memory.

[BibT_eX]

[DOI]

IEEE Access, 2020

Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges.

[BibT_eX]

[DOI]

Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Spin-Based Reconfigurable Logic for Power- and Area-Efficient Applications.

[BibT_eX]

[DOI]

IEEE Des. Test, 2019

Toward Physically Unclonable Functions from Plasmonics-Enhanced Silicon Disc Resonators.

[BibT_eX]

[DOI]

CoRR, 2019

An Interposer-Based Root of Trust: Seize the Opportunity for Secure System-Level Integration of Untrusted Chiplets.

[BibT_eX]

[DOI]

CoRR, 2019

3D Integration: Another Dimension Toward Hardware Security.

[BibT_eX]

[DOI]

Satwik Patnaik

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Attacking Split Manufacturing from a Deep Learning Perspective.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Protect Your Chip Design Intellectual Property: An Overview.

[BibT_eX]

[DOI]

Satwik Patnaik

Proceedings of the International Conference on Omni-Layer Intelligent Systems, 2019

2018

Multi-Objective 3D Floorplanning with Integrated Voltage Assignment.

[BibT_eX]

[DOI]

Ibrahim Abe M. Elfadel

ACM Trans. Design Autom. Electr. Syst., 2018

Best of both worlds: integration of split manufacturing and camouflaging into a security-driven CAD flow for 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

Advancing hardware security using polymorphic and stochastic spin-hall effect devices.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Raise your game for split manufacturing: restoring the true functionality through BEOL.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

Concerted wire lifting: Enabling secure and cost-effective split manufacturing.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Optimal die placement for interposer-based 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration.

[BibT_eX]

[DOI]

Ibrahim Abe M. Elfadel

Cliff C. N. Sze

IPSJ Trans. Syst. LSI Des. Methodol., 2017

Rethinking split manufacturing: An information-theoretic approach with secure layout techniques.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

On Mitigation of Side-Channel Attacks in 3D ICs: Decorrelating Thermal Patterns from Power and Activity.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

Physical Design Automation for 3D Chip Stacks: Challenges and Solutions.

[BibT_eX]

[DOI]

Proceedings of the 2016 on International Symposium on Physical Design, 2016

2015

Planning Massive Interconnects in 3-D Chips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2014

Structural planning of 3D-IC interconnects by block alignment.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Utilizing 2D and 3D rectilinear blocks for efficient IP reuse and floorplanning of 3D-integrated systems.

[BibT_eX]

[DOI]

Robert Fischbach

Proceedings of the International Symposium on Physical Design, 2013

Integration of thermal management and floorplanning based on three-dimensional layout representations.

[BibT_eX]

[DOI]

Puskar Budhathoki

Andreas Henschel

Ibrahim Abe M. Elfadel

Proceedings of the 20th IEEE International Conference on Electronics, 2013

2012

Assembling 2-D Blocks Into 3-D Chips.

[BibT_eX]

[DOI]

Igor L. Markov

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Multiobjective optimization of deadspace, a critical resource for 3D-IC integration.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011

Assembling 2D blocks into 3D chips.

[BibT_eX]

[DOI]

Igor L. Markov

Proceedings of the 2011 International Symposium on Physical Design, 2011

Investigating modern layout representations for improved 3d design automation.

[BibT_eX]

[DOI]

Robert Fischbach