Johann Hauer

According to our database1, Johann Hauer authored at least 30 papers between 2001 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2017
A case study on dynamic control of complex operational amplifier performance using back gate biasing.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

2016
A 83dB SNDR low power readout ASIC for piezoresistive nanogauge based gyroscopes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A SIC design of an implantable system for improved control of hand prosthesis.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

2015
A versatile analog front-end for sensors based on piezoresistive silicon nanowire detection.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Current Feedback Linearization Applied to Oscillator Based ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

144 Channel measurement IC for CdZnTe sensors with energy and time resolution.
Microelectron. J., 2014

Wireless bi-directional data link for an EEG recording system using STM32.
Proceedings of the 2014 IEEE International Symposium on Medical Measurements and Applications, 2014

2013
144 channel measurement IC for CZT sensors with energy and time resolution.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2013

An inverter-based 6-bit pipelined ADC with low power consumption.
Proceedings of Eurocon 2013, 2013

2012
A low power oscillator based TDC with in-system non-linearity correction.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A mixed-signal front-end ASIC for EEG acquisition system.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
Modeling and experimental results of short channel annular MOS transistors.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2009
A dc <i>I</i>-<i>V</i> model for short-channel polygonal enclosed-layout transistors.
Int. J. Circuit Theory Appl., 2009

Erstellung und Verifizierung eines VHDL-AMS-Modells für einen kapazitiven Delta-Sigma-Modulator.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2009

A low-power continuous-time incremental 2nd-order-MASH ΣΔ-modulator for a CMOS imager.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

A study of CMOS radiation tolerant transistors using green functions.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Prospect of the future of switched-current circuits with regard to future CMOS technologies.
Microelectron. J., 2008

A flexible algorithmic ADC for wireless sensor nodes.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Low-Noise Sigma-Delta Capacitance-to-Digital Converter for Sub-pF Capacitive Sensors with Integrated Dielectric Loss Measurement.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
A 92dB-DR 13mW ΔΣ Modulator for Spaceborn Fluxgate Sensors.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Improved Analytical I-V model for polygonal-shape enclosed layout transistors.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2005
Performance analysis of high-speed MOS transistors with different layout styles.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Practical considerations on doughnut transistors design.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

1.8-V second-order ΣΔ modulator in 0.18-μm CMOS technology.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2003
Current Mode CMOS Synthesis of a Motor-Control Neural System.
Proceedings of the Artificial Neural Nets Problem Solving Methods, 2003

An Analogue Current-Mode Hardware Design Proposal for Preprocessing Layers in ART-Based Neural Networks.
Proceedings of the Artificial Neural Nets Problem Solving Methods, 2003

A 16-bit 60μW multi-bit ΣΔ modulator for portable ECG applications.
Proceedings of the ESSCIRC 2003, 2003

2001
A successive approximation A/D converter with 16 bit 200 kS/s in 0.6 μm CMOS using self calibration and low power techniques.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Fast CMOS current driver for IrDA - applications.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001


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