Johan Raman

Orcid: 0000-0002-6130-1734

According to our database1, Johan Raman authored at least 22 papers between 1999 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
A Double-Edge Triggered Asynchronous Gray Counter for Use as a Coarse Counter in VCO ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2024

Origin of Frequency-Dependent Distortion and Calibration for Ring Oscillator VCO ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2024

A 3.5 GS/s 1-1 MASH VCO ADC With Second-Order Noise Shaping.
CoRR, 2024

2022
A 2 MS/s Full Bandwidth Hall System with Low Offset Enabled by Randomized Spinning.
Sensors, 2022

A Fast Offset Reduction Loop Based on a Bilinear Integrator for Sensor Readout Circuits.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

First-order Hold DAC Reconstruction Filtering for Efficient Image Rejection.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2019
Low-Pass Filtering SC-DAC for Reduced Jitter and Slewing Requirements on CTSDMs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Current-Mode Floating-Bridge Technique for Closed-Loop ΣΔ Readout of Wheatstone Bridge Sensors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Experimental results on PWM linearization of a VCO-ADC with 3rd order noise shaping.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Passive Loop Filter Assistance for CTSDMs.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

2012
A very compact 1MS/s Nyquist-rate A/D-converter with 12 effective bits.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2008
An Unconstrained Architecture for Systematic Design of Higher Order SigmaDelta Force-Feedback Loops.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

An On-Line Calibration Technique for Mismatch Errors in High-Speed DACs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

2007
An Unconstrained Architecture for High-Order Sigma Delta Force-Feedback Inertial Sensors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2005
STF behaviour in a CT ΔΣ modulator.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

2004
Systematic design of double-sampling Sigma Delta ADC's with modified NTF.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
An approach to tackle quantization noise folding in double-sampling ΣΔ modulation A/D converters.
IEEE Trans. Circuits Syst. II Express Briefs, 2003

2002
An efficient technique to eliminate quantisation noise folding in double-sampling Sigma-Delta modulators.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Composite functions in an orthogonal polynomial base.
Signal Process., 2001

2000
Time domain adaptive delay estimation.
IEEE Trans. Signal Process., 2000

1999
On noise suppression in adaptive delay estimation.
Proceedings of the ISSPA '99. Proceedings of the Fifth International Symposium on Signal Processing and its Applications, 1999

Adaptive fractional delay estimation without lock-up.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999


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