Joel Hestness
Orcid: 0000-0001-6920-0906
According to our database1,
Joel Hestness
authored at least 28 papers
between 2009 and 2024.
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Bibliography
2024
Normalization Layer Per-Example Gradients are Sufficient to Predict Gradient Noise Scale in Transformers.
CoRR, 2024
Sparse maximal update parameterization: A holistic approach to sparse training dynamics.
CoRR, 2024
Proceedings of the Findings of the Association for Computational Linguistics, 2024
2023
Cerebras-GPT: Open Compute-Optimal Language Models Trained on the Cerebras Wafer-Scale Cluster.
CoRR, 2023
Proceedings of the Sixth Conference on Machine Learning and Systems, 2023
2022
2021
Proceedings of the Fourth Conference on Machine Learning and Systems, 2021
2020
Memory Efficient 3D U-Net with Reversible Mobile Inverted Bottlenecks for Brain Tumor Segmentation.
Proceedings of the Brainlesion: Glioma, Multiple Sclerosis, Stroke and Traumatic Brain Injuries, 2020
2019
Proceedings of the 24th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2019
Proceedings of the 2019 Conference on Empirical Methods in Natural Language Processing and the 9th International Joint Conference on Natural Language Processing, 2019
2017
Proceedings of the 18th Annual Conference of the International Speech Communication Association, 2017
2015
GPU Computing Pipeline Inefficiencies and Optimization Opportunities in Heterogeneous CPU-GPU Processors.
Proceedings of the 2015 IEEE International Symposium on Workload Characterization, 2015
2014
A comparative analysis of microarchitecture effects on CPU and GPU memory system behavior.
Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014
2012
2011
Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011
2010
Proceedings of the Third International Workshop on Network on Chip Architectures, 2010
2009
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009