João Navarro

According to our database, João Navarro authored at least 6 papers between 2013 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

A Divide-by-1.5/2 Prescaler Utilizing Double Data Rate Technique.

Lucas Daudt Franck, João Navarro, João Paulo Carmo

Proceedings of the 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design, 2024

2021

Charge-Pump Circuit in 65nm CMOS for Neural Stimulation on Deep-Brain Stimulation.

Tiago Mateus Nordi, V. M. Barbosa, R. H. Gounella, Godfred Asan, Maximiliam Luppe, João Navarro, Soares Junior, Joao Paulo Carmo, Erich Talamoni Fonoff, Eduardo Colombari

Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021

2020

Performance Comparison of High-Speed Dual Modulus Prescalers Using Metaheuristic Sizing/Optimization.

João Navarro, Maximiliam Luppe

Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

2019

Design of a low power 10-bit 12MS/s asynchronous SAR ADC in 65nm CMOS.

Arthur Lombardi Campos, João Navarro, Maximiliam Luppe

Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019

2014

Design for Stability of Active Inductor with Feedback Resistance.

Gabriel R. Guerreiro, João Navarro

Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

2013

A power optimized decimator for sigma-delta data converters.

Dionisio de Carvalho, João Navarro

Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013