JoAnn M. Paul

According to our database1, JoAnn M. Paul authored at least 40 papers between 1995 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2017
Building Maze Solutions with Computational Dreaming.
IEEE Micro, 2017

2015
Multiprocessor Capacity Metric and Analysis.
IEEE Trans. Computers, 2015

Chip-level programming of heterogeneous multiprocessors.
Proceedings of the 10th International Design & Test Symposium, 2015

2013
Contextual partitioning for speech recognition.
ACM Trans. Embed. Comput. Syst., 2013

2012
Workload Mode Identification for Chip Heterogeneous Multiprocessors.
Int. J. Parallel Program., 2012

2011
Capacity metric for chip heterogeneous multiprocessors.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

2010
Stochastic Contention Level Simulation for Single-Chip Heterogeneous Multiprocessors.
IEEE Trans. Computers, 2010

2009
The Emerging Landscape of Computer Performance Evaluation.
Adv. Comput., 2009

2008
Interrupt modeling for efficient high-level scheduler design space exploration.
ACM Trans. Design Autom. Electr. Syst., 2008

Holistic design and caching in mobile computing.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

Webpage-based benchmarks for mobile device design.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Amdahl's Law Revisited for Single Chip Systems.
Int. J. Parallel Program., 2007

A New Era of Performance Evaluation.
Computer, 2007

Shared Resource Access Attributes for High-Level Contention Models.
Proceedings of the 44th Design Automation Conference, 2007

Event-based re-training of statistical contention models for heterogeneous multiprocessors.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

2006
Scenario-oriented design for single-chip heterogeneous multiprocessors.
IEEE Trans. Very Large Scale Integr. Syst., 2006

What's in a Name.
Computer, 2006

2005
High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors.
ACM Trans. Design Autom. Electr. Syst., 2005

Undergraduate embedded system education at Carnegie Mellon.
ACM Trans. Embed. Comput. Syst., 2005

Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors.
IEEE Trans. Computers, 2005

Scenario-Oriented Design for Single Chip Heterogeneous Multiprocesso.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

2004
Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach.
Proceedings of the 2004 Design, 2004

High level cache simulation for heterogeneous multiprocessors.
Proceedings of the 41th Design Automation Conference, 2004

Benchmark-based design strategies for single chip heterogeneous multiprocessors.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003
Layered, Multi-Threaded, High-Level Performance Design.
Proceedings of the 2003 Design, 2003

Schedulers as model-based design elements in programmable heterogeneous multiprocessors.
Proceedings of the 40th Design Automation Conference, 2003

Programmers' views of SoCs.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

2002
System-Level Modeling of a Network Switch SoC.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Multi-Level Modeling of Software on Hardware in Concurrent Computation.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems.
Proceedings of the 2002 Design, 2002

The design context of concurrent computation systems.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

2001
Co-RAM: combinational logic synthesis applied to software partitions for mapping to a novel memory device.
IEEE Trans. Very Large Scale Integr. Syst., 2001

Modeling and simulation of steady state and transient behaviors for emergent SoCs.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Modeling and evaluation of hardware/software designs.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

2000
A codesign virtual machine for hierarchical, balanced hardware/software system modeling.
Proceedings of the 37th Conference on Design Automation, 2000

Frequency interleaving as a codesign scheduling paradigm.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

1999
Peer-based multithreaded executable co-specification.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1996
Load Balancing Using Heterogeneous Processors for Continuum Problems on a Mesh.
J. Parallel Distributed Comput., 1996

1995
The Dynamic Analysis of MIMD Architectures.
Proceedings of the Seventh IASTED/ISMM International Conference on Parallel and Distributed Computing and Systems, 1995

Dynamic Communication and Architecture of Parallel Processors.
Proceedings of the Seventh IASTED/ISMM International Conference on Parallel and Distributed Computing and Systems, 1995


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