Joan Figueras
According to our database1,
Joan Figueras
authored at least 124 papers
between 1991 and 2020.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2020
Indirect and adaptive test of analogue circuits based on preselected steady-state response measures.
IET Circuits Devices Syst., 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
2017
Multi-Directional Space Tessellation to Improve the Decision Boundary in Indirect Mixed-Signal Testing.
J. Electron. Test., 2017
Proceedings of the 22nd IEEE European Test Symposium, 2017
2016
Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents.
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Efficient Production Binning Using Octree Tessellation in the Alternate Measurements Space.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Integr., 2016
2015
Proceedings of the 20th IEEE European Test Symposium, 2015
STT-MRAM cell reliability evaluation under process, voltage and temperature (PVT) variations.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Skew violation verification in digital interconnect signals based on signal addition.
IEICE Electron. Express, 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Proceedings of the 19th IEEE European Test Symposium, 2014
Proceedings of the 19th IEEE European Test Symposium, 2014
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
2013
Diagnosis of Interconnect Full Open Defects in the Presence of Gate Leakage Currents.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Proceedings of the 18th IEEE European Test Symposium, 2013
Proceedings of the 18th IEEE European Test Symposium, 2013
2012
Efficiency evaluation of parametric failure mitigation techniques for reliable SRAM operation.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Unidirectional error detection, localization and correction for DRAMs: Application to on-line DRAM repair strategies.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis.
Proceedings of the 15th European Test Symposium, 2010
Proceedings of the 15th European Test Symposium, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Verifying Functional Specifications by Regression Techniques on Lissajous Test Signatures.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
Proceedings of the 2008 IEEE International Test Conference, 2008
2007
Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
2006
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
2005
J. Electron. Test., 2005
Proceedings of the 10th European Test Symposium, 2005
2004
J. Electron. Test., 2004
J. Electron. Test., 2004
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004
Proceedings of the 9th European Test Symposium, 2004
2003
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003
On the selection of efficient arithmetic additive test pattern generators [logic test].
Proceedings of the 8th European Test Workshop, 2003
Proceedings of the 8th European Test Workshop, 2003
2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
On High-Quality, Low Energy BIST Preparation at RT-Level.
Proceedings of the 3rd Latin American Test Workshop, 2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
2001
J. Electron. Test., 2001
J. Electron. Test., 2001
Dynamic Signal X-Y Zoning and its Applicability to Detect Time Critical Defects in the Digital Domain.
Proceedings of the 2nd Latin American Test Workshop, 2001
Test Challenges in a Nanometric World.
Proceedings of the 2nd Latin American Test Workshop, 2001
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001
2000
J. Electron. Test., 2000
An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family.
J. Electron. Test., 2000
J. Electron. Test., 2000
Some Experiments in Test Pattern Generation for FPGA-Implemented Combinational Circuits.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000
Detectability Dependency on Test Generation Process for Interconnection Opens.
Proceedings of the 1st Latin American Test Workshop, 2000
Test Configuration Generation for FPGA Logic Cells.
Proceedings of the 1st Latin American Test Workshop, 2000
Proceedings of the 5th European Test Workshop, 2000
TOF: a tool for test pattern generation optimization of an FPGA application oriented test.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
1999
Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999
Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study.
Proceedings of the 4th European Test Workshop, 1999
Proceedings of the 1999 Design, 1999
Proceedings of the 1999 Design, 1999
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999
1998
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
Proceedings of the Field-Programmable Logic and Applications, 1998
Proceedings of the 1998 Design, 1998
Proceedings of the 1998 Design, 1998
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998
1997
VLSI Design, 1997
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997
Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model.
Proceedings of the European Design and Test Conference, 1997
Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997
1996
J. Electron. Test., 1996
Dynamic characterization of Built-In Current Sensors based on PN junctions: Analysis and experiments.
J. Electron. Test., 1996
Enhancing realistic fault secureness in parity prediction array arithmetic operators by I<sub>DDQ</sub> monitoring.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996
Achieving Fault Secureness in Parity Prediction Arithmetic Operators: General Conditions and Implementations.
Proceedings of the 1996 European Design and Test Conference, 1996
Proceedings of the 1996 European Design and Test Conference, 1996
1995
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995
Synthesis of I<sub>DDQ</sub>-testable circuits: integrating built-in current sensors.
Proceedings of the 1995 European Design and Test Conference, 1995
Proceedings of the 1995 European Design and Test Conference, 1995
1994
Electrical model of the floating gate defect in CMOS ICs: implications on I<sub>DDQ</sub> testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994
Analysis of Bridging Defects in Sequential CMOS Circuits and their Current Testability.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
1993
Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993
Test Generation with High Coverages for Quiescent Current Test of Bridging Faults in Combinational Circuits.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993
Current Testing Viability in Dynamic CMOS Circuits.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993
Analysis of the Floating Gate Defect in CMOS.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993
1992
J. Electron. Test., 1992
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992
1991
Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991