Joakim Urdahl
According to our database1,
Joakim Urdahl
authored at least 12 papers
between 2010 and 2020.
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Bibliography
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
2019
Exploiting Hardware Unobservability for Low-Power Design and Safety Analysis in Formal Verification-Driven Design Flows.
IEEE Trans. Very Large Scale Integr. Syst., 2019
2018
Symbolic quick error detection using symbolic initial state for pre-silicon verification.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017
2016
PhD thesis, 2016
Properties first? a new design methodology for hardware, and its perspectives in safety analysis.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
2015
Architectural System Modeling for Correct-by-Construction RTL Design.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2015
2014
Path Predicate Abstraction for Sound System-Level Models of RT-Level Circuit Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
T4B: Formal verification in system-on-chip design: Scientific foundations and practical methodology.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
2013
Formal system-on-chip verification: An operation-based methodology and its perspectives in low power design.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013
2012
System verification of concurrent RTL modules by compositional path predicate abstraction.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2010
Proceedings of 10th International Conference on Formal Methods in Computer-Aided Design, 2010