Joachim Neves Rodrigues
According to our database1,
Joachim Neves Rodrigues
authored at least 58 papers
between 2001 and 2024.
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Bibliography
2024
Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024
2022
An 88% fractional bandwidth reconfigurable power amplifier for NB-IoT and LTE-M in 22 nm CMOS FDSOI.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2022, Oslo, 2022
2021
An Energy-Efficient Near-Memory Computing Architecture for CNN Inference at Cache Level.
Proceedings of the 28th IEEE International Conference on Electronics, 2021
Proceedings of the 47th ESSCIRC 2021, 2021
2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IET Comput. Digit. Tech., 2018
2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Improving practical sensitivity of energy optimized wake-up receivers: proof of concept in 65nm CMOS.
CoRR, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3V 7T sense-amplifierless SRAM in 28 nm FD-SOI.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
IEEE Trans. Biomed. Circuits Syst., 2015
Microprocess. Microsystems, 2015
A 128-channel discrete cosine transform-based neural signal processor for implantable neural recording microsystems.
Int. J. Circuit Theory Appl., 2015
Digital background calibration in continuous-time delta-sigma analog to digital converters.
Proceedings of the Nordic Circuits and Systems Conference, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Ultra low energy and area efficient charge pump with automatic clock controller in 65 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015
2014
Proceedings of the 8th International Symposium on Medical Information and Communication Technology, 2014
A low-complex peak-to-average power reduction scheme for OFDM based massive MIMO systems.
Proceedings of the 6th International Symposium on Communications, 2014
Hardware efficient approximative matrix inversion for linear pre-coding in massive MIMO.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014
A 35 fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOS.
Proceedings of the ESSCIRC 2014, 2014
2013
Ultra low energy design exploration of digital decimation filters in 65 nm dual-V<sub>T</sub> CMOS in the sub-V<sub>T</sub> domain.
Microprocess. Microsystems, 2013
Approximative matrix inverse computations for very-large MIMO and applications to linear pre-coding systems.
Proceedings of the 2013 IEEE Wireless Communications and Networking Conference (WCNC), 2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Proceedings of the 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, 2013
Proceedings of the ESSCIRC 2013, 2013
2012
Ultra-Low-Power Error Correction Circuits: Technology Scaling and Sub-V<sub>T</sub> Operation.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
High-Level Energy Estimation in the Sub-V$_{{\rm T}}$ Domain: Simulation and Measurement of a Cardiac Event Detector.
IEEE Trans. Biomed. Circuits Syst., 2012
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012
An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing.
Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012
TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
Proceedings of the 38th European Solid-State Circuit conference, 2012
2011
Energy-minimum sub-threshold self-timed circuits using current-sensing completion detection.
IET Comput. Digit. Tech., 2011
Benchmarking of Standard-Cell Based Memories in the Sub- V<sub>T</sub> Domain in 65-nm CMOS Technology.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
Highly scalable implementation of a robust MMSE channel estimator for OFDM multi-standard environment.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011
Reconfigurable cell array for concurrent support of multiple radio standards by flexible mapping.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
2010
Microprocess. Microsystems, 2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
A sign-bit auto-correlation architecture for fractional frequency offset estimation in OFDM.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Hardware Implementation of an Iterative Sampling Rate Converter for Wireless Communication.
Proceedings of the Global Communications Conference, 2010
Minimum-Energy Sub-threshold Self-Timed Circuits: Design Methodology and a Case Study.
Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems, 2010
2009
Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-V<sub><i>t</i></sub> Domain By Architectural Folding.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
2005
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005
Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005
A dual-mode wavelet based R-wave detector using single-V<sub>t</sub> for leakage reduction [cardiac pacemaker applications].
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
A wavelet based R-wave detector for cardiac pacemakers in 0.35 CMOS technology.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2001
QRS detection for pacemakers in a noisy environment using a time lagged artificial neural network.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001