Jizhong Shen
Orcid: 0000-0002-9031-2379
According to our database1,
Jizhong Shen
authored at least 28 papers
between 1990 and 2024.
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Bibliography
2024
An efficient algorithm for estimating gate-level power consumption in large-scale integrated circuits.
Microelectron. J., 2024
2023
2022
FreSCo: Frequency-Domain Scan Context for LiDAR-based Place Recognition with Translation and Rotation Invariance.
CoRR, 2022
Localization of seizure onset zone with epilepsy propagation networks based on graph convolutional network.
Biomed. Signal Process. Control., 2022
FreSCo: Frequency-Domain Scan Context for LiDAR-based Place Recognition with Translation and Rotation Invariance.
Proceedings of the 17th International Conference on Control, 2022
2021
J. Inf. Secur. Appl., 2021
2020
IEEE Trans. Inf. Forensics Secur., 2020
Web page classification based on heterogeneous features and a combination of multiple classifiers.
Frontiers Inf. Technol. Electron. Eng., 2020
2019
Detection method of domain names generated by DGAs based on semantic representation and deep neural network.
Comput. Secur., 2019
P300-based deception detection of mock network fraud with modified genetic algorithm and combined classification.
Proceedings of the 7th International Winter Conference on Brain-Computer Interface, 2019
2018
An Intrusion Detection System Using a Deep Neural Network With Gated Recurrent Units.
IEEE Access, 2018
2017
Function synthesis algorithm based on RTD-based three-variable universal logic gates.
Frontiers Inf. Technol. Electron. Eng., 2017
An algorithm for identifying symmetric variables based on the order eigenvalue matrix.
Frontiers Inf. Technol. Electron. Eng., 2017
Sci. China Inf. Sci., 2017
Improved low-entropy masking scheme for LED with mitigation against correlation-enhanced collision attacks.
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017
2016
Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme.
Frontiers Inf. Technol. Electron. Eng., 2016
An Algorithm for Identifying Symmetric Variables in the Canonical Reed-Muller Algebra System.
J. Circuits Syst. Comput., 2016
Design of flip-flops with clock-gating and pull-up control scheme for power-constrained and speed-insensitive applications.
IET Comput. Digit. Tech., 2016
2015
Frontiers Inf. Technol. Electron. Eng., 2015
J. Appl. Math., 2015
2012
Microelectron. J., 2012
2011
Microelectron. J., 2011
J. Zhejiang Univ. Sci. C, 2011
1996
1995
Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995
1993
1992
Fuzzifying Topological Groups Based on Completely Distributive Residuated Lattice-Valued Logic (I).
Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992
1990