Jize Jiang
Orcid: 0000-0002-8889-3784
According to our database1,
Jize Jiang
authored at least 10 papers
between 2014 and 2024.
Collaborative distances:
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Bibliography
2024
UOUO: Uncontextualized Uncommon Objects for Measuring Knowledge Horizons of Vision Language Models.
Proceedings of the 2024 Conference on Empirical Methods in Natural Language Processing, 2024
2023
2018
A 65-nm CMOS Low Dropout Regulator Featuring >60-dB PSRR Over 10-MHz Frequency Range and 100-mA Load Current Range.
IEEE J. Solid State Circuits, 2018
Radiation Hardening By Design Integrated Circuits Enabling Low-Cost Satellites for Internet-of-Things.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018
2017
A 5.6 ppm/°C Temperature Coefficient, 87-dB PSRR, Sub-1-V Voltage Reference in 65-nm CMOS Exploiting the Zero-Temperature-Coefficient Point.
IEEE J. Solid State Circuits, 2017
2016
Experimental investigation into radiation-hardening-by-design (RHBD) flip-flop designs in a 65nm CMOS process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
A novel subthreshold voltage reference featuring 17ppm/°C TC within -40°C to 125°C and 75dB PSRR.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
Radiation-hardened library cell template and its total ionizing dose (TID) delay characterization in 65nm CMOS process.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014