Jiun-Lang Huang

Proceedings of the IEEE International Test Conference in Asia, 2022

Intelligent Design Automation for Heterogeneous Integration.

[BibT_eX]

[DOI]

Iris Hui-Ru Jiang

Yao-Wen Chang

Charlie Chung-Ping Chen

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

2021

Opportunities for 2.5/3D Heterogeneous SoC Integration.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021

Automatic Test Program Generation for Transition Delay Faults in Pipelined Processors.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2021

2020

DSSP-ATPG: A Deterministic Search-Space Parallel Test Pattern Generator.

[BibT_eX]

[DOI]

Kuen-Wei Yeh

Proceedings of the IEEE International Test Conference in Asia, 2020

Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Functional-Like Transition Delay Fault Test-Pattern Generation using a Bayesian-Based Circuit Model.

[BibT_eX]

[DOI]

Ching-Yuan Chen

Ching-Hong Cheng

Krishnendu Chakrabarty

Proceedings of the IEEE European Test Symposium, 2020

2019

An FPGA-Based Data Receiver for Digital IC Testing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2019

Testability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime.

[BibT_eX]

[DOI]

Kai-Hsun Chen

Ching-Yuan Chen

Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

Reinforcement-Learning-Based Test Program Generation for Software-Based Self-Test.

[BibT_eX]

[DOI]

Ching-Yuan Chen

Proceedings of the 28th IEEE Asian Test Symposium, 2019

2018

Conference Reports: Report on 2017 IEEE Asian Test Symposium.

[BibT_eX]

[DOI]

Jin-Fu Li

IEEE Des. Test, 2018

A Multi-Fault Dynamic Compaction Technique for Test Pattern Count Reduction.

[BibT_eX]

[DOI]

Bo-Yi Li

Proceedings of the International SoC Design Conference, 2018

Design and Implementation of an FPGA-Based 16-Channel Data/Timing Formatter.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017

Source code transformation for software-based on-line error detection.

[BibT_eX]

[DOI]

Tsung-Yen Tsai

Proceedings of the IEEE Conference on Dependable and Secure Computing, 2017

Design and Implementation of an EG-Pool Based FPGA Formatter with Temperature Compensation.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator.

[BibT_eX]

[DOI]

Kuen-Wei Yeh

Laung-Terng Wang

J. Electron. Test., 2016

An IR-Drop Aware Test Pattern Generator for Scan-Based At-Speed Testing.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015

Design, Automation, and Test for Low-Power and Reliable Flexible Electronics.

[BibT_eX]

[DOI]

Tsung-Ching Jim Huang

Found. Trends Electron. Des. Autom., 2015

Design and Implementation of an FPGA-Based Data/Timing Formatter.

[BibT_eX]

[DOI]

J. Electron. Test., 2015

A test-application-count based learning technique for test time reduction.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design, Automation and Test, 2015

SDC-TPG: A Deterministic Zero-Inflation Parallel Test Pattern Generator.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014

FPGA-Based Subset Sum Delay Lines.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Synergistic Reliability and Yield Enhancement Techniques for Embedded SRAMs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Improve speed path identification with suspect path expressions.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

A circular pipeline processing based deterministic parallel test pattern generator.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Test Conference, 2013

An IDDQ-based source driver IC design-for-test technique.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

A mutual characterization based SAR ADC self-testing technique.

[BibT_eX]

[DOI]

H.-J. Lin

Proceedings of the 18th IEEE European Test Symposium, 2013

Fault Scrambling Techniques for Yield Enhancement of Embedded Memories.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

2012

Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2012

An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration.

[BibT_eX]

[DOI]

J. Electron. Test., 2012

A SAR ADC missing-decision level detection and removal technique.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

A Transition Isolation Scan Cell Design for Low Shift and Capture Power.

[BibT_eX]

[DOI]

Yi-Tsung Lin

Xiaoqing Wen

Proceedings of the 21st IEEE Asian Test Symposium, 2012

A Built-In Characterization Technique for 1-Bit/Stage Pipelined ADC.

[BibT_eX]

[DOI]

Y.-H. Chou

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011

ADC/DAC Loopback Linearity Testing by DAC Output Offsetting and Scaling.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Histogram-Based Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCs.

[BibT_eX]

[DOI]

J. Electron. Test., 2011

Robust Circuit Design for Flexible Electronics.

[BibT_eX]

[DOI]

Tsung-Ching Huang

IEEE Des. Test Comput., 2011

A Promising Alternative to Conventional Silicon.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2011

Clock-gating-aware low launch WSA test pattern generation for at-speed scan testing.

[BibT_eX]

[DOI]

Yi-Tsung Lin

Xiaoqing Wen

Proceedings of the 2011 IEEE International Test Conference, 2011

A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager.

[BibT_eX]

[DOI]

Proceedings of the 16th European Test Symposium, 2011

A self-testing and calibration method for embedded successive approximation register ADC.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

CSER: BISER-based concurrent soft-error resilience.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

An ADC/DAC loopback testing methodology by DAC output offsetting and scaling.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

A scalable quantitative measure of IR-drop effects for scan pattern generation.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

A robust ADC code hit counting technique.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

An error tolerance scheme for 3D CMOS imagers.

[BibT_eX]

[DOI]

Hsiu-Ming Chang

Ding-Ming Kwai

Cheng-Wen Wu

Proceedings of the 47th Design Automation Conference, 2010

Power Supply Noise Reduction in Broadcast-Based Compression Environment for At-speed Scan Testing.

[BibT_eX]

[DOI]

Chun-Yong Liang

Proceedings of the 19th IEEE Asian Test Symposium, 2010

Improved weight assignment for logic switching activity during at-speed test pattern generation.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A Charge-Sensing-Capable Source Driver for TFT Array Testing in System-on-Panel Displays.

[BibT_eX]

[DOI]

Chen-Wei Lin

J. Comput., 2009

LPTest: a Flexible Low-Power Test Pattern Generator.

[BibT_eX]

[DOI]

Kai-Shun Hu

J. Electron. Test., 2009

An On-Chip Integrator Leakage Characterization Technique and Its Application to Switched Capacitor Circuits Testing.

[BibT_eX]

[DOI]

Chen-Yuan Yang

Proceedings of the Eighteentgh Asian Test Symposium, 2009

Diagnosing integrator leakage of single-bit first-order DeltaSigma modulator using DC input.

[BibT_eX]

[DOI]

Chen-Yuan Yang

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

A Built-In TFT Array Charge-Sensing Technique for System-on-Panel Displays.

[BibT_eX]

[DOI]

Chen-Wei Lin

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Scan Testing in Huffman Coding Test Compression Environment.

[BibT_eX]

[DOI]

Yi-Tsung Lin

Proceedings of the 17th IEEE Asian Test Symposium, 2008

Testing LCD Source Driver IC with Built-on-Scribe-Line Test Circuitry.

[BibT_eX]

[DOI]

Chiuan-Che Li

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

An Efficient Peak Power Reduction Technique for Scan Testing.

[BibT_eX]

[DOI]

Kai-Shun Hu

Proceedings of the 16th Asian Test Symposium, 2007

2006

A Low-Cost Jitter Measurement Technique for BIST Applications.

[BibT_eX]

[DOI]

Yuan-Shuang Liu

J. Electron. Test., 2006

On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines.

[BibT_eX]

[DOI]

J. Electron. Test., 2006

A Random Jitter Extraction Technique in the Presence of Sinusoidal Jitter.

[BibT_eX]

[DOI]

Proceedings of the 15th Asian Test Symposium, 2006

A routability constrained scan chain ordering technique for test power reduction.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Random Jitter Testing Using Low Tap-Count Delay Lines.

[BibT_eX]

[DOI]

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

An Infrastructure IP for On-Chip Clock Jitter Measurement.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

2003

Practical considerations in applying Σ-Δ modulation-based analog BIST to sampled-data systems.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2003

A Low-Cost Jitter Measurement Technique for BIST Applications.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

On-chip Analog Response Extraction with 1-Bit ? - Modulators.

[BibT_eX]

[DOI]

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

2000

Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-Test.

[BibT_eX]

[DOI]

Jan Arild Tofte

Chee-Kian Ong

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Testing and characterization of the one-bit first-order delta-sigma modulator for on-chip analog signal analysis.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

A BIST Scheme for On-Chip ADC and DAC Testing.

[BibT_eX]

[DOI]

Chee-Kian Ong

Proceedings of the 2000 Design, 2000

A sigma-delta modulation based BIST scheme for mixed-signal circuits.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

1999

Specification Back-Propagation and Its Application to DC Fault Simulation for Analog/Mixed-Signal Circuits.

[BibT_eX]

[DOI]

Chen-Yang Pan

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

1997

Analog Fault Diagnosis for Unpowered Circuit Boards.

[BibT_eX]

[DOI]