Jiu Xiong

According to our database, Jiu Xiong authored at least 7 papers between 2017 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

A Continuous-Time Sigma-Delta Modulator With Continuous-Time Delay-Based Integrator.

Jiu Xiong, Jin Liu, Hoi Lee

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 3^rd Order CT-ΣΔ Modulator with a Hybrid Loop Filter Employing Passive and Continuous-Time Delay Based Integrators.

Jiu Xiong, Jeniffer Zhao, Jin Liu, Hoi Lee

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2019

An 8-b 2b/cycle Asynchronous SAR ADC with Capacitive Divider Based RC-DAC.

Jiu Xiong, Jiajun Ren, Jin Liu

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

ADC Quantization with Overlapping Metastability Zones and Dual Reference Calibration.

Jiajun Ren, Jiu Xiong, Jin Liu

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

2018

High-Speed ADC Quantization with Overlapping Metastability Zones.

Jiajun Ren, Jiu Xiong, Jin Liu

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017

An open-loop 28GHz 16-phase clock generator in 28nm CMOS.

Jiu Xiong, Jin Liu, Yucheng Dai, Hlaing Minn

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A New Receiver Architecture for MIMO Beam-Forming Applications.

Yucheng Dai, Yahia R. Ramadan, Hlaing Minn, Jiu Xiong, Jin Liu, Alan Gatherer

Proceedings of the 2017 IEEE Global Communications Conference, 2017