Jithendra Srinivas

According to our database1, Jithendra Srinivas authored at least 6 papers between 2008 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
Reactive tiling.
Proceedings of the 13th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2015

2013
Locality-aware mapping and scheduling for multicores.
Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization, 2013

2011
Compiler Directed Data Locality Optimization for Multicore Architectures.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
Clock gating approaches by IOEX graphs and cluster efficiency plots.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Clock gating effectiveness metrics: Applications to power optimization.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008
Clock gating for power optimization in ASIC design cycle theory & practice.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008


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