Jitendra Khare

According to our database1, Jitendra Khare authored at least 20 papers between 1992 and 2006.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2006
Embedded Memory Field Returns - Trials and Tribulations.
Proceedings of the 2006 IEEE International Test Conference, 2006

2004
Memory Yield Improvement - SoC Design Perspective.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Test Strategies For a 40Gbps Framer SoC.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003
DFM - A Fabless Perspective.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2001
Enabling Embedded Memory Diagnosis via Test Response Compression.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000
Test and Debug of Networking SoCs: A Case Study.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Manufacturability and Testability Oriented Synthesis.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Maximizing Wafer Productivity Through Layout Optimization.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Cost Trade-Offs in System On Chip Designs.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1998
Design-Manufacturing Interface: Part II - Applications.
Proceedings of the 1998 Design, 1998

Design-Manufacturing Interface: Part I - Vision.
Proceedings of the 1998 Design, 1998

Manufacturability analysis of standard cell libraries.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1997
CAD at the Design-Manufacturing Interface.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Fault characterization of standard cell libraries using inductive contamination.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Design for manufacturability in submicron domain.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1995
Testability-oriented channel routing.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Inductive Contamination Analysis (ICA) with SRAM Application.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1993
Estimation of reject ratio in testing of combinatorial circuits.
Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

1992
Design for testability view on placement and routing.
Proceedings of the conference on European design automation, 1992


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