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Jisu Yook

According to our database1, Jisu Yook authored at least 2 papers in 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization.
[BibTeX]
[DOI]
Jahoon Jin
,
Soo-Min Lee
,
Kyunghwan Min
,
Sodam Ju
,
Jihoon Lim
,
Jisu Yook
,
Jihoon Lee
,
Hyunsu Chae
,
Kwonwoo Kang
,
Yunji Hong
,
Yeongcheol Jeong
,
Sungsik Park
,
Sang-Ho Kim
,
Jongwoo Lee
,
Joonsuk Kim
,
Sung-Ung Kwak
IEEE J. Solid State Circuits, January, 2024

A 20Gb/s/pin Single-Ended PAM-4 Transceiver with Pre/Post-Channel Switching Jitter Compensation and DQS-Driven Biasing for Low-Power Memory Interfaces.
[BibTeX]
[DOI]
Kyunghwan Min
,
Jahoon Jin
,
Soo-Min Lee
,
Sodam Ju
,
Jisu Yook
,
Jihoon Lee
,
Yunji Hong
,
Sungsik Park
,
Sang-Ho Kim
,
Jongwoo Lee
,
Hyungjong Ko
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024


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