Jishun Kuang

Orcid: 0000-0001-9451-7980

According to our database1, Jishun Kuang authored at least 34 papers between 2003 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
The design of ΔΣ-ADC in MEMS gyro interface ASIC.
Microelectron. J., April, 2023

2022
Small-Signal Processing Low-Overhead Operational Amplifier for delta-Sigma ADC.
J. Circuits Syst. Comput., 2022

2021
Improving Compression Ratios for Code-Based Test Pattern Compressions through Column-Wise Reordering Algorithms.
J. Circuits Syst. Comput., 2021

2019
LPCMsim: A Lightweight Phase Change Memory Simulator.
Future Gener. Comput. Syst., 2019

A Pseudo-Random Transform Decomposition Method for Improving the Coding Compression Ratio of Test Data.
Proceedings of the 21st IEEE International Conference on High Performance Computing and Communications; 17th IEEE International Conference on Smart City; 5th IEEE International Conference on Data Science and Systems, 2019

Design and Implementation of GPU Accelerated Active Storage in FastDFS.
Proceedings of the 21st IEEE International Conference on High Performance Computing and Communications; 17th IEEE International Conference on Smart City; 5th IEEE International Conference on Data Science and Systems, 2019

2018
A novel memristor-based restricted Boltzmann machine for contrastive divergence.
IEICE Electron. Express, 2018

2016
Representative Scan Architecture.
J. Circuits Syst. Comput., 2016

A parallel-SSHI rectifier for ultra-low-voltage piezoelectric vibration energy harvesting.
IEICE Electron. Express, 2016

A sort method to enhance significant spectral components of test set.
Proceedings of the 12th International Conference on Natural Computation, 2016

2015
An efficient small-delay faults simulator based on critical path tracing.
Int. J. Circuit Theory Appl., 2015

Logic operation-based DFT method and 1R memristive crossbar March-like test algorithm.
IEICE Electron. Express, 2015

An active rectifier with optimal flip timing for the internal capacitor for piezoelectric vibration energy harvesting.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Improve the compression ratios for code-based test vector compressions by decomposing.
Proceedings of the 20th IEEE European Test Symposium, 2015

2014
An adaptive neural network A/D converter based on CMOS/memristor hybrid design.
IEICE Electron. Express, 2014

2013
Comparator and half adder design using complementary resistive switches crossbar.
IEICE Electron. Express, 2013

2012
Achieving low capture and shift power in linear decompressor-based test compression environment.
Microelectron. J., 2012

Virtual scan chains reordering using a RAM-based module for high test compression.
Microelectron. J., 2012

A scan disabling-based BAST scheme for test cost and test power reduction.
IEICE Electron. Express, 2012

Switching activity reduction for scan-based BIST using weighted scan input data.
IEICE Electron. Express, 2012

2011
Test data compression using interval broadcast scan for embedded cores.
Microelectron. J., 2011

A New Test Data Compression Scheme.
J. Comput., 2011

A scan disabling-based BAST scheme for test cost reduction.
IEICE Electron. Express, 2011

Test Data Compression Using Selective Sparse Storage.
J. Electron. Test., 2011

2010
Test Data Compression Using Four-Coded and Sparse Storage for Testing Embedded Core.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2010

Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
Small Delay Fault Simulation for Sequential Circuits.
Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

2008
Test Response Data Volume and Wire Length Reductions for Extended Compatibilities Scan Tree Construction.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

A Novel BIST Scheme Using Test Vectors Applied by Circuit-under-Test Itself.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

DCScan: A Power-Aware Scan Testing Architecture.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2005
A New BIST Solution for System-on-Chip.
Proceedings of the 11th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2005), 2005

2003
IDDT: Fundamentals and Test Generation.
J. Comput. Sci. Technol., 2003

At-Speed Current Testing.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

IDDT ATPG Based on Ambiguous Delay Assignments.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003


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