Jiro Naganuma

According to our database, Jiro Naganuma authored at least 22 papers between 1988 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2012

An H.264/AVC High422 Profile and MPEG-2 422 Profile Encoder LSI for HDTV Broadcasting Infrastructures.

Koyo Nitta, Hiroe Iwasaki, Takayuki Onishi, Takashi Sano, Atsushi Sagata, Yasuyuki Nakajima, Minoru Inamori, Ryuichi Tanida, Atsushi Shimizu, Ken Nakamura, Mitsuo Ikeda, Jiro Naganuma

IEICE Trans. Electron., 2012

2010

MPEG-2 Transcoding Method for Reducing Re-quantization Noise Based on a Two-tiered Quantizer Matrix.

Takeshi Yoshitome, Jiro Naganuma, Yoshiyuki Yashima

Inf. Media Technol., 2010

2008

A Flexible Video CODEC System for Super High Resolution Video.

Takeshi Yoshitome, Ken Nakamura, Jiro Naganuma, Yoshiyuki Yashima

IEICE Trans. Inf. Syst., 2008

A Distributed Stream Multiplexing Architecture for Multi-Chip Configuration beyond HDTV.

Takayuki Onishi, Ken Nakamura, Takeshi Yoshitome, Jiro Naganuma

IEICE Trans. Inf. Syst., 2008

Multi-reference and multi-block-size motion estimation with flexible mode selection for professional 4: 2: 2 H.264/AVC encoder LSI.

Takayuki Onishi, Takashi Sano, Koyo Nitta, Mitsuo Ikeda, Jiro Naganuma

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007

Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level.

Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Toshihiro Minami, Makoto Endo, Yoshiyuki Yashima

IEEE Trans. Very Large Scale Integr. Syst., 2007

2006

Highly accurate de-jittering scheme for broadcast quality video transmission.

Takayuki Onishi, Mitsuo Ikeda, Jiro Naganuma, Makoto Endo, Yoshiyuki Yashima

Syst. Comput. Jpn., 2006

2005

New set-top box for interactive visual communication of home entertainment using MPEG-2 full-duplex CODEC LSI.

Minoru Inamori, Hiroe Iwasaki, Takayuki Onishi, Mitsuo Ikeda, Jiro Naganuma, Yoshiyuki Yashima

IEEE Trans. Consumer Electron., 2005

MPEG-2 real-time software CODEC for full-duplex transmission application over IP networks.

Hiroe Iwasaki, Jiro Naganuma, Makoto Endo, Yoshiyuki Yashima

Syst. Comput. Jpn., 2005

2004

A distributed TS-MUX architecture for multi-chip extension beyond the HDTV level.

Takayuki Onishi, Mitsuo Ikeda, Jiro Naganuma, Makoto Endo, Yoshiyuki Yashima

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level.

Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Makoto Endo

Proceedings of the 2003 Design, 2003

A 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems.

Hiroe Iwasaki, Jiro Naganuma, Yasuyuki Nakajima, Yutaka Tashiro, Ken Nakamura, Takeshi Yoshitome, Takayuki Onishi, Mitsuo Ikeda, Takaaki Izuoka, Makoto Endo

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002

Advanced concurrent design environment for multimedia system LSIs.

Hiroe Iwasaki, Katsuyuki Ochiai, Jiro Naganuma, Makoto Endo, Takeshi Ogura

Syst. Comput. Jpn., 2002

1999

A memory-based architecture for MPEG2 system protocol LSIs.

Minoru Inamori, Jiro Naganuma, Makoto Endo

IEEE Trans. Very Large Scale Integr. Syst., 1999

SuperENC: MPEG-2 video encoder chip.

Mitsuo Ikeda, Toshio Kondo, Koyo Nitta, Kazuhito Suguri, Takeshi Yoshitome, Toshihiro Minami, Hiroe Iwasaki, Katsuyuki Ochiai, Jiro Naganuma, Makoto Endo, Yutaka Tashiro, Hiroshi Watanabe, Naoki Kobayashi, Tsuneo Okubo, Ryota Kasai

IEEE Micro, 1999

On-Chip Multimedia Real-Time OS and its MPEG-2 Applications.

Hiroe Iwasaki, Jiro Naganuma, Makoto Endo, Takeshi Ogura

Proceedings of the 6th International Workshop on Real-Time Computing and Applications Symposium (RTCSA '99), 1999

High-speed Software-based Platform for Embedded Software of a Single-chip MPEG-2 Video Encoder LSI with HDTV Scalabilit.

Katsuyuki Ochiai, Hiroe Iwasaki, Jiro Naganuma, Makoto Endo, Takeshi Ogura

Proceedings of the 1999 Design, 1999

An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture.

Mitsuo Ikeda, Toshio Kondo, Koyo Nitta, Kazuhito Suguri, Takeshi Yoshitome, Toshihiro Minami, Jiro Naganuma, Takeshi Ogura

Proceedings of the 1999 Design, 1999

1996

A Memory-based Architecture for MPEG2 System Protocol LSIs.

Minoru Inamori, Jiro Naganuma, Haruo Wakabayashi, Makoto Endo

Proceedings of the 1996 European Design and Test Conference, 1996

1994

A Highly OR-Parallel Inference Machine (Multi-ASCA) and Its Performance Evaluation: An Architecture and Its Load Balancing Algorithms.

Jiro Naganuma, Takeshi Ogura

IEEE Trans. Computers, 1994

High-Level Design Validation Using Algorithmic Debugging.

Jiro Naganuma, Takeshi Ogura, Tamio Hoshino

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1988

High-Speed CAM-Based Architecture for a Prolog Machine (ASCA).

Jiro Naganuma, Takeshi Ogura, Shin-Ichiro Yamada, Takashi Kimura

IEEE Trans. Computers, 1988