Jiro Kishimoto
According to our database1,
Jiro Kishimoto
authored at least 5 papers
between 2001 and 2024.
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Bibliography
2024
13.7 A 1Tb Density 3b/Cell 3D-NAND Flash on a 2YY-Tier Technology with a 300MB/s Write Throughput.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2010
A temperature compensation word-line voltage generator for multi-level cell NAND Flash memories.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2001
IEEE J. Solid State Circuits, 2001