Jirí Matousek

Orcid: 0000-0002-9447-0366

Affiliations:
  • Brno University of Technology, Czech Republic


According to our database1, Jirí Matousek authored at least 14 papers between 2011 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2023
Accelerating IDS Using TLS Pre-Filter in FPGA.
Proceedings of the IEEE Symposium on Computers and Communications, 2023

2022
ClassBench-ng: Benchmarking Packet Classification Algorithms in the OpenFlow Era.
IEEE/ACM Trans. Netw., 2022

2021
Scalability of Hash-Based Pattern Matching for High-Speed Network Security and Monitoring.
Proceedings of the IEEE Symposium on Computers and Communications, 2021

Increasing Memory Efficiency of Hash-Based Pattern Matching for High-Speed Networks.
Proceedings of the International Conference on Field-Programmable Technology, 2021

2020
Increasing Throughput of Intrusion Detection Systems by Hash-Based Short String Pre-filter.
Proceedings of the 45th IEEE Conference on Local Computer Networks, 2020

2019
Deep Packet Inspection in FPGAs via Approximate Nondeterministic Automata.
CoRR, 2019

Deep Packet Inspection in FPGAs via Approximate Nondeterministic Automata.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2018
High-Speed Regular Expression Matching with Pipelined Memory-Based Automata.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

Regular expression matching with pipelined delayed input DFAs for high-speed networks.
Proceedings of the 2018 Symposium on Architectures for Networking and Communications Systems, 2018

2017
ClassBench-ng: Recasting ClassBench after a Decade of Network Evolution.
Proceedings of the ACM/IEEE Symposium on Architectures for Networking and Communications Systems, 2017

2014
Fast lookup for dynamic packet filtering in FPGA.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2013
Memory efficient IP lookup in 100 GBPS networks.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Towards hardware architecture for memory efficient IPv4/IPv6 Lookup in 100 Gbps networks.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2011
Precise IPv4/IPv6 packet generator based on NetCOPE platform.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011


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