Jiri Jenícek

According to our database, Jiri Jenícek authored at least 19 papers between 2006 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2020

Feasibility of OFDM and FHSS in a Single Home Automation and Security Network.

Tomás Jakubík, Jiri Jenícek

Proceedings of the 43rd International Conference on Telecommunications and Signal Processing, 2020

2019

SDR All-channels Receiver for FHSS Sensor Network in Cortex-M.

Tomás Jakubík, Jiri Jenícek

Proceedings of the 42nd International Conference on Telecommunications and Signal Processing, 2019

2017

Sequential Test Decompressors with Fast Tester Bits Wide-Spreading.

Ondrej Novák, Jiri Jenícek, Martin Rozkovec

J. Circuits Syst. Comput., 2017

2016

Test Decompressor Effectivity Improvement.

Ondrej Novák, Jiri Jenícek, Martin Rozkovec

Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Sequential test decompressors with fast variable wide spreading.

Ondrej Novák, Jiri Jenícek, Martin Rozkovec

Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015

Test compression for circuits with multiple scan chains.

Ondrej Novák, Jiri Jenícek, Martin Rozkovec

Proceedings of the 16th Latin-American Test Symposium, 2015

LFSR Reseeding Based Test Compression Respecting Different Controllability of Decompressor Outputs.

Ondrej Novák, Jiri Jenícek, Martin Rozkovec

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014

Test-data compression with low number of channels and short test time.

Ondrej Novák, Jiri Jenícek, Martin Rozkovec

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2013

Test pattern decompression in parallel scan chain architecture.

Martin Chloupek, Jiri Jenícek, Ondrej Novák, Martin Rozkovec

Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012

An evaluation of the application dependent FPGA test method.

Martin Rozkovec, Jiri Jenícek, Ondrej Novák

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

On test time reduction using pattern overlapping, broadcasting and on-chip decompression.

Martin Chloupek, Ondrej Novák, Jiri Jenícek

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011

Advanced scan chain configuration method for broadcast decompressor architecture.

Jiri Jenícek, Ondrej Novák, Martin Chloupek

Proceedings of the 9th East-West Design & Test Symposium, 2011

Test vector overlapping based compression tool for narrow test access mechanism.

Jiri Jenícek, Martin Rozkovec, Ondrej Novák

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2010

Application dependent FPGA testing method using compressed deterministic test vectors.

Martin Rozkovec, Jiri Jenícek, Ondrej Novák

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

COMPAS - Advanced test compressor.

Jiri Jenícek, Ondrej Novák

Proceedings of the 2010 East-West Design & Test Symposium, 2010

Application Dependent FPGA Testing Method.

Martin Rozkovec, Jiri Jenícek, Ondrej Novák

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2008

Efficient Test Pattern Compression Method Using Hard Fault Preferring.

Jiri Jenícek

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007

Test Pattern Compression Based on Pattern Overlapping.

Jiri Jenícek, Ondrej Novák

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006

Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead.

Ondrej Novák, Zdenek Plíva, Jiri Jenícek, Zbynek Mader, Michal Jarkovský

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006