Jiongyao Ye

Orcid: 0000-0003-2625-5848

According to our database1, Jiongyao Ye authored at least 15 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Links

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Bibliography

2024
A Low-Latency Noise-Aware Tone Mapping Operator for Hardware Implementation with a Locally Weighted Guided Filter.
Symmetry, March, 2024

FDTNet: Enhancing frequency-aware representation for prohibited object detection from X-ray images via dual-stream transformers.
Eng. Appl. Artif. Intell., 2024

2023
A multimodal transformer to fuse images and metadata for skin disease classification.
Vis. Comput., July, 2023

Perceiving Multiple Representations for scene text image super-resolution guided by text recognizer.
Eng. Appl. Artif. Intell., 2023

2022
Cross-Domain Attention and Center Loss for Sketch Re-Identification.
IEEE Trans. Inf. Forensics Secur., 2022

2019
A Low-power Shared Cache Design with Modified PID Controller for Efficient Multicore Embedded Systems.
J. Inf. Process., 2019

2018
A Novel Real-time Highway Visibility Measurement System Based on Dark Channel Prior.
Proceedings of the 2018 International Conference on Image and Graphics Processing, 2018

2017
Integrating operation scheduling and binding for functional unit power-gating in high-level synthesis.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2015
Application-specific shared last-level cache optimization for low-power embedded systems.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

2013
Pseudo Dual Path Processing to reduce the branch misprediction penalty in embedded processors.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
A Behavior-based Adaptive Access-mode for Low-power Set-associative Caches in Embedded Systems.
J. Inf. Process., 2012

2011
A New Recovery Mechanism in Superscalar Microprocessors by Recovering Critical Misprediction.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

An Adaptive Various-Width Data Cache for Low Power Design.
IEICE Trans. Inf. Syst., 2011

Analysis before Starting an Access: A New Power-Efficient Instruction Fetch Mechanism.
IEICE Trans. Inf. Syst., 2011

A behavior-based reconfigurable cache for the low-power embedded processor.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011


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