Jiong Luo

According to our database, Jiong Luo authored at least 21 papers between 2000 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Improving LUT-based optimization for ASICs.

Walter Lau Neto, Luca G. Amarù, Vinicius Possani, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

LUT-Based Optimization For ASIC Design Flow.

Luca Gaetano Amarù, Vinicius N. Possani, Eleonora Testa, Felipe S. Marranghello, Christopher Casares, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

SAT-Sweeping Enhanced for Logic Synthesis.

Luca G. Amarù, Felipe S. Marranghello, Eleonora Testa, Christopher Casares, Vinicius N. Possani, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Scalable Boolean Methods in a Modern Synthesis Flow.

Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Jiong Luo, Christopher Casares, Pierre-Emmanuel Gaillardon, Giovanni De Micheli

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

Integrated ESOP Refactoring for Industrial Designs.

Winston Haaswijk, Luca Gaetano Amarù, Patrick Vuillod, Jiong Luo, Mathias Soeken, Giovanni De Micheli

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Improvements to boolean resynthesis.

Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Janet Olson, Robert K. Brayton, Giovanni De Micheli

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Enabling exact delay synthesis.

Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon, Janet Olson, Robert K. Brayton, Giovanni De Micheli

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Logic optimization and synthesis: Trends and directions in industry.

Luca Gaetano Amarù, Patrick Vuillod, Jiong Luo, Janet Olson

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Multi-level logic benchmarks: An exactness study.

Luca Gaetano Amarù, Mathias Soeken, Winston Haaswijk, Eleonora Testa, Patrick Vuillod, Jiong Luo, Pierre-Emmanuel Gaillardon, Giovanni De Micheli

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2007

Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems.

Jiong Luo, Niraj K. Jha, Li-Shiuan Peh

IEEE Trans. Very Large Scale Integr. Syst., 2007

Power-Efficient Scheduling for Heterogeneous Distributed Real-Time Embedded Systems.

Jiong Luo, Niraj K. Jha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2005

Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems.

Le Yan, Jiong Luo, Niraj K. Jha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

2004

Register binding-based RTL power management for control-flow intensive designs.

Jiong Luo, Lin Zhong, Yunsi Fei, Niraj K. Jha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

2003

Power-profile Driven Variable Voltage Sealing for Heterogeneous Distributed Real-time Embedded Systems.

Jiong Luo, Niraj K. Jha

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems.

Le Yan, Jiong Luo, Niraj K. Jha

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

A comprehensive high-level synthesis system for control-flow intensive behaviors.

Weidong Wang, Tat Kee Tan, Jiong Luo, Yunsi Fei, Li Shang, Keith S. Vallerio, Lin Zhong, Anand Raghunathan, Niraj K. Jha

Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

2002

Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems.

Jiong Luo, Niraj K. Jha

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors.

Lin Zhong, Jiong Luo, Yunsi Fei, Niraj K. Jha

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Low Power Distributed Embedded Systems: Dynamic Voltage Scaling and Synthesis.

Jiong Luo, Niraj K. Jha

Proceedings of the High Performance Computing, 2002

2001

Battery-Aware Static Scheduling for Distributed Real-Time Embedded Systems.

Jiong Luo, Niraj K. Jha

Proceedings of the 38th Design Automation Conference, 2001

2000

Power-Conscious Joint Scheduling of Periodic Task Graphs and Aperiodic Tasks in Distributed Real-Time Embedded Systems.

Jiong Luo, Niraj K. Jha

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000