Jinzheng Tu

Orcid: 0000-0003-4080-1876

Affiliations:
  • Princeton University, Princeton, NJ, USA


According to our database1, Jinzheng Tu authored at least 5 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2023
DECADES: A 67mm<sup>2</sup>, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

CIFER: A 12nm, 16mm<sup>2</sup>, 22-Core SoC with a 1541 LUT6/mm<sup>2</sup> 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022
OPDB: A Scalable and Modular Design Benchmark.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2020
OpenPiton at 5: A Nexus for Open and Agile Hardware Design.
IEEE Micro, 2020

2017
Exploring Efficient Strategies for Minesweeper.
Proceedings of the Workshops of the The Thirty-First AAAI Conference on Artificial Intelligence, 2017


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