Jinjiang Yang
Orcid: 0000-0003-4934-806X
According to our database1,
Jinjiang Yang
authored at least 19 papers
between 2012 and 2024.
Collaborative distances:
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Bibliography
2024
IEEE Trans. Dependable Secur. Comput., 2024
16.2 A 28nm 69.4kOPS 4.4μJ/Op Versatile Post-Quantum Crypto-Processor Across Multiple Mathematical Problems.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
Research on Performance Optimization of Encryption Algorithms for Network Security Framework.
Proceedings of the 2024 3rd International Conference on Cyber Security, 2024
Proceedings of the 2024 on ACM SIGSAC Conference on Computer and Communications Security, 2024
2022
More is Less: Domain-Specific Speech Recognition Microprocessor Using One-Dimensional Convolutional Recurrent Neural Network.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
An energy-efficient dynamically reconfigurable cryptographic engine with improved power/EM-side-channel-attack resistance.
Sci. China Inf. Sci., 2022
Forward Private Multi-Client Searchable Encryption with Efficient Access Control in Cloud Storage.
Proceedings of the IEEE Global Communications Conference, 2022
2020
Proceedings of the ICCSP 2020: 4th International Conference on Cryptography, 2020
2018
EERA-DNN: An energy-efficient reconfigurable architecture for DNNs with hybrid bit-width and logarithmic multiplier.
IEICE Electron. Express, 2018
Proceedings of the 17th IEEE International Conference On Trust, 2018
An Energy-efficient Reconfigurable Hybrid DNN Architecture for Speech Recognition with Approximate Computing.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018
2017
Context Management Scheme Optimization of Coarse-Grained Reconfigurable Architecture for Multimedia Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2017
E-ERA: An energy-efficient reconfigurable architecture for RNNs using dynamically adaptive approximate computing.
IEICE Electron. Express, 2017
Proceedings of the 2017 IEEE Symposium Series on Computational Intelligence, 2017
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017
2016
An area-efficient design of reconfigurable S-box for parallel implementation of block ciphers.
IEICE Electron. Express, 2016
High performance and area efficiency design of global register file for coarse-grained reconfigurable cryptographic processor.
IEICE Electron. Express, 2016
A Novel Design of Pipeline MDC-FFT Processor Based on Various Memory Access Mechanism.
Proceedings of the International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2016
2012
Hybrid-Priority Configuration Cache Supervision Method for Coarse Grained Reconfigurable Architecture.
Proceedings of the 2012 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2012