Jinian Bian

According to our database, Jinian Bian authored at least 85 papers between 1997 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

Adaptive Selection and Clustering of Partial Reconfiguration Modules for Modern FPGA Design Flow.

Kang Zhao, Yuchun Ma, Ruining He, Jixing Zhang, Ning Xu, Jinian Bian

ACM Trans. Reconfigurable Technol. Syst., June, 2023

2013

Unification of PR Region floorplanning and Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs.

Ruining He, Guoqiang Liang, Yuchun Ma, Yu Wang, Jinian Bian

J. Circuits Syst. Comput., 2013

RALP: Reconvergence-aware layer partitioning for 3D FPGAs.

Qingyu Liu, Yuchun Ma, Yu Wang, Wayne Luk, Jinian Bian

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

FPGA IP protection by binding Finite State Machine to Physical Unclonable Function.

Jiliang Zhang, Yaping Lin, Yongqiang Lyu, Gang Qu, Ray C. C. Cheung, Wenjie Che, Qiang Zhou, Jinian Bian

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Binding Hardware IPs to Specific FPGA Device via Inter-twining the PUF Response with the FSM of Sequential Circuits.

Jiliang Zhang, Yaping Lin, Yongqiang Lu, Ray C. C. Cheung, Wenjie Che, Qiang Zhou, Jinian Bian

Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Automatic enhanced CDFG generation based on runtime instrumentation.

Zhongda Yuan, Yuchun Ma, Jinian Bian, Kang Zhao

Proceedings of the 2013 IEEE 17th International Conference on Computer Supported Cooperative Work in Design (CSCWD), 2013

Efficient custom instruction generation based on characterizing of basic blocks.

Guoqiang Liang, Yuchun Ma, Kang Zhao, Jinian Bian

Proceedings of the 2013 IEEE 17th International Conference on Computer Supported Cooperative Work in Design (CSCWD), 2013

Data dependency aware prefetch scheduling for Dynamic Partial reconfigurable designs.

Jixin Zhang, Ning Xu, Yuchun Ma, Yu Wang, Jinian Bian

Proceedings of the IEEE 10th International Conference on ASIC, 2013

Incremental 3D NoC synthesis based on physical-aware router merging algorithm.

Yuanyuan Li, Ning Xu, Yuchun Ma, Jinian Bian

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012

UNISM: Unified Scheduling and Mapping for General Networks on Chip.

Ou He, Sheqin Dong, Wooyoung Jang, Jinian Bian, David Z. Pan

IEEE Trans. Very Large Scale Integr. Syst., 2012

Pruning-Based Trace Signal Selection Algorithm for Data Acquisition in Post-Silicon Validation.

Kang Zhao, Jinian Bian

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

SMPP: Generic SAT Solver over Reconfigurable Hardware Accelerator.

Zhongda Yuan, Yuchun Ma, Jinian Bian

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

RAW Introduction.

Jürgen Becker, Jinian Bian, Christophe Bobda, René Cumplido, Michael Hübner

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

ISBA: An independent set-based algorithm for automated partial reconfiguration module generation.

Ruining He, Yuchun Ma, Kang Zhao, Jinian Bian

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

PDPR: Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs.

Ruining He, Guoqiang Liang, Yuchun Ma, Yu Wang, Jinian Bian

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011

Buffer Planning for IP Placement Using Sliced-LFF.

Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto

VLSI Design, 2011

Processor Accelerator Customization through Data Flow Graph Exploration.

Kang Zhao, Jinian Bian

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

A fast recursive detailed routing algorithm for hierarchical FPGAs.

Limin Zhu, Jinian Bian, Qiang Zhou, Yici Cai

Proceedings of the 2011 15th International Conference on Computer Supported Cooperative Work in Design, 2011

Instruction-level hardware/software partition through DFG exploration.

Kang Zhao, Jinian Bian

Proceedings of the 2011 15th International Conference on Computer Supported Cooperative Work in Design, 2011

Pruning-based trace signal selection algorithm.

Kang Zhao, Jinian Bian

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Multilevel Optimization for Large-Scale Hierarchical FPGA Placement.

Hui Dai, Qiang Zhou, Jinian Bian

J. Comput. Sci. Technol., 2010

Mutation-based diagnostic test generation for hardware design error diagnosis.

Shujun Deng, Kwang-Ting Cheng, Jinian Bian, Zhiqiu Kong

Proceedings of the 2011 IEEE International Test Conference, 2010

A low power clock network placement framework.

Dawei Liu, Qiang Zhou, Yongqiang Lu, Jinian Bian

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Wirelength-driven force-directed 3D FPGA placement.

Wentao Sui, Sheqin Dong, Jinian Bian

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Bus via reduction based on floorplan revising.

Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Behavioral level dual-vth design for reduced leakage power with thermal awareness.

Junbo Yu, Qiang Zhou, Gang Qu, Jinian Bian

Proceedings of the Design, Automation and Test in Europe, 2010

An architecture-aware routing optimization via satisfiabilty for hierarchical FPGA.

Limin Zhu, Qiang Zhou, Yici Cai, Jinian Bian

Proceedings of the 2010 14th International Conference on Computer Supported Cooperative Work in Design, 2010

Peeling algorithm for custom instruction identification.

Kang Zhao, Jinian Bian

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009

Pipeline-Based Partition Exploration for Heterogeneous Multiprocessor Synthesis.

Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Constrained Stimulus Generation with Self-Adjusting Using Tabu Search with Memory.

Yanni Zhao, Jinian Bian, Shujun Deng, Zhiqiu Kong, Kang Zhao

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Peak Temperature Reduction by Physical Information Driven Behavioral Synthesis with Resource Usage Allocation.

Junbo Yu, Qiang Zhou, Gang Qu, Jinian Bian

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Cell shifting aware of wirelength and overlap.

Dawei Liu, Qiang Zhou, Jinian Bian, Yici Cai, Xianlong Hong

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Random stimulus generation with self-tuning.

Yanni Zhao, Jinian Bian, Shujun Deng, Zhiqiu Kong

Proceedings of the 13th International Conference on Computers Supported Cooperative Work in Design, 2009

Global density smoothing technique for analytical placement algorithm.

Dawei Liu, Qiang Zhou, Jinian Bian, Yanming Jia

Proceedings of the 11th International Conference on Computer-Aided Design and Computer Graphics, 2009

Fast placement for large-scale hierarchical FPGAs.

Hui Dai, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong

Proceedings of the 11th International Conference on Computer-Aided Design and Computer Graphics, 2009

An approach to synthesis delay semantics in VHDL.

Lixin Cheng, Jinian Bian, Yunyun Liu

Proceedings of the 11th International Conference on Computer-Aided Design and Computer Graphics, 2009

Peak temperature control in thermal-aware behavioral synthesis through allocating the number of resources.

Junbo Yu, Qiang Zhou, Jinian Bian

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Self-adjusting constrained random stimulus generation using splitting evenness evaluation and XOR constraints.

Shujun Deng, Zhiqiu Kong, Jinian Bian, Yanni Zhao

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Exploring Partitions Based on Search Space Smoothing for Heterogeneous Multiprocessor System.

Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Fast Custom Instruction Identification Algorithm Based on Basic Convex Pattern Model for Supporting ASIP Automated Design.

Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

A cooperative universal data model platform for the data-centric electronic system-level design.

Kun Tong, Jinian Bian, Haili Wang

Adv. Eng. Informatics, 2008

Automated Specific Instruction Customization Methodology for Multimedia Processor Acceleration.

Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

A novel fixed-outline floorplanner with zero deadspace for hierarchical design.

Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

HyMacs: hybrid memory access optimization based on custom-instruction scheduling.

Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation.

Xing Wei, Juanjuan Chen, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong

Proceedings of the FPL 2008, 2008

Cache miss reduction through hardware-assisted loop optimization.

Kang Zhao, Jinian Bian, Chenqian Jiang, Sheqin Dong, Satoshi Goto

Proceedings of the 12th International Conference on CSCW in Design, 2008

Low power clock buffer planning methodology in F-D placement for large scale circuit design.

Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning.

Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan.

Zhipeng Liu, Jinian Bian, Qiang Zhou, Hui Dai

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

An effective buffer planning algorithm for IP based fixed-outline SOC placement.

Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

EHSAT: An Efficient RTL Satisfiability Solver Using an Extended DPLL Procedure.

Shujun Deng, Jinian Bian, Weimin Wu, Xiaoqing Yang, Yanni Zhao

Proceedings of the 44th Design Automation Conference, 2007

A Fast Custom Instructions Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design.

Kang Zhao, Jinian Bian, Sheqin Dong

Proceedings of the 11th International Conference on Computer Supported Cooperative Work in Design, 2007

A Management System of Metropolis Energy Information.

Hui Zhang, Jinian Bian

Proceedings of the 11th International Conference on Computer Supported Cooperative Work in Design, 2007

VPH: Versatile Routability-Driven Place Algorithm for Hierarchical FPGAs Based on VPR.

Yanhua Wang, Qiang Zhou, Jinian Bian, Junhua Qu

Proceedings of the 10th International Conference on Computer-Aided Design and Computer Graphics, 2007

Power-driven Real-time System Design with Energy Efficiency via ISA Customization.

Chenqian Jiang, Jinian Bian, Kang Zhao

Proceedings of the 10th International Conference on Computer-Aided Design and Computer Graphics, 2007

EHSAT Modeling from Algorithm Description for RTL Model Checking.

Xiaoqing Yang, Jinian Bian, Shujun Deng, Yanni Zhao

Proceedings of the 16th Asian Test Symposium, 2007

2006

Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration.

Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani

ACM Trans. Design Autom. Electr. Syst., 2006

Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization.

Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

A novel collaborative scheme of simulation and model checking for system properties verification.

Ming Zhu, Jinian Bian, Weimin Wu

Comput. Ind., 2006

A Heterogeneous Dependency Graph as Intermediate Representation for Instruction Set Customization.

Kang Zhao, Jinian Bian, Sheqin Dong

Proceedings of the 2006 Joint Conference on Information Sciences, 2006

Integrating dynamic thermal via planning with 3D floorplanning algorithm.

Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng

Proceedings of the 2006 International Symposium on Physical Design, 2006

Universal data model platform: the data-centric evolution for system level codesign.

Kun Tong, Jinian Bian, Haili Wang

Proceedings of the 10th International Conference on CSCW in Design, 2006

AGOM: A Novel Method of Embedded System Communication Architecture Design in System Level Design.

Yawen Niu, Jinian Bian, Haili Wang, Kun Tong, Liang Zhu

Proceedings of the 10th International Conference on CSCW in Design, 2006

An Efficient Cooperative Design Framework for SOC On-Chip Communication Architecture System-Level Design.

Yawen Niu, Jinian Bian, Haili Wang, Kun Tong

Proceedings of the Computer Supported Cooperative Work in Design III, 2006

Bounded Model Checking Combining Symbolic Trajectory Evaluation Abstraction with Hybrid Three-Valued SAT Solving.

Shujun Deng, Weimin Wu, Jinian Bian

Proceedings of the Computer Supported Cooperative Work in Design III, 2006

Cooperative Bounded Model Checking Using STE and Hybrid Three-Valued SAT Solving.

Shujun Deng, Weimin Wu, Jinian Bian

Proceedings of the 10th International Conference on CSCW in Design, 2006

From Software to Hardware - A Novel TLM Auto-Generating Method.

Liang Zhu, Jinian Bian

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

High Level Synthesis with Multiple supply Voltages for Energy and Combined Peak Power Minimization.

Zhen Zhao, Jinian Bian, Zhipeng Liu, Yunfeng Wang, Kang Zhao

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

A Clustering ILP Model for Fast Instruction Selection in Embedded Applicated Specific Processor Design.

Kang Zhao, Jinian Bian

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

Interconnect delay optimization via high level re-synthesis after floorplanning.

Yunfeng Wang, Jinian Bian, Xianlong Hong

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation.

Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design.

Yunfeng Wang, Jinian Bian, Xianlong Hong, Liu Yang, Qiang Zhou, Qiang Wu

Proceedings of the Embedded Software and Systems, Second International Conference, 2005

HW/SW Interface Synthesis Based on Avalon Bus Specification for Nios-Oriented SoC Design.

Feng Lin, Haili Wang, Jinian Bian

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Cooperation of SMV and Jeda for the property checking of mixed control and data intensive designs.

Jianzhou Zhao, Jinian Bian, Weimin Wu

Proceedings of the Ninth International Conference on Computer Supported Cooperative Work in Design, 2005

iTuCoMe: HCDFG-based incremental tuning HW/SW co-design methodology for multi-level exploration.

Haili Wang, Jinian Bian, Qiang Wu, Yunfeng Wang

Proceedings of the Ninth International Conference on Computer Supported Cooperative Work in Design, 2005

System-level architectural exploration using allocation-on-demand technique.

Qiang Wu, Jinian Bian, Hongxi Xue

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Model Optimization Techniques in a Verification Platform for Classified Properties.

Ming Zhu, Jinian Bian, Weimin Wu

Proceedings of the Embedded Software and Systems, First International Conference, 2004

A Distributed Architecture Model for Heterogeneous Multiprocessor System-on-Chip Design.

Qiang Wu, Jinian Bian, Hongxi Xue

Proceedings of the Embedded Software and Systems, First International Conference, 2004

CA-Ex: A Tuning-Incremental Methodology for Communication Architectures in Embedded Systems.

Haili Wang, Jinian Bian, Yawen Niu, Kun Tong, Yunfeng Wang

Proceedings of the Embedded Software and Systems, First International Conference, 2004

PFGASAT- A Genetic SAT Solver Combining Partitioning and Fuzzy Strategie.

Jianzhou Zhao, Jinian Bian, Weimin Wu

Proceedings of the 28th International Computer Software and Applications Conference (COMPSAC 2004), 2004

2003

Property Classification for Functional Verification Based.

Ming Zhu, Jinian Bian, Weimin Wu, Hongxi Xue

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Accelerating Logic Rewiring Using Implication Analysis Tree.

Chin Ngai Sze, Wangning Long, Yu-Liang Wu, Jinian Bian

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

2000

IBAW: an implication-tree based alternative-wiring logic transformation algorithm.

Wangning Long, Yu-Liang Wu, Jinian Bian

Proceedings of ASP-DAC 2000, 2000

1999

FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking.

Jinsong Bei, Hongxing Li, Jinian Bian, Hongxi Xue, Xianlong Hong

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1997

VIDE: a visual VHDL integrated design environment.

Jinian Bian, Hongxi Xue, Ming Su

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997