Jinhua Cui
Orcid: 0000-0002-3252-7937Affiliations:
- Huazhong University of Science and Technology, Wuhan, China
- Xi'an Jiaotong University, China (Ph.D., 2018)
According to our database1,
Jinhua Cui
authored at least 23 papers
between 2014 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
Optimizing Secure Deletion in Interlaced Magnetic Recording With Move-on-Cover Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024
IEEE Trans. Netw. Sci. Eng., 2024
SmartNetSSD: Exploiting Path Resources for Read Performance Improvement in Network-Based SSDs.
Proceedings of the 42nd IEEE International Conference on Computer Design, 2024
2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023
IEEE Trans. Parallel Distributed Syst., 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Proceedings of the Network and Parallel Computing, 2022
2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
2020
Leveraging partial-refresh for performance and lifetime improvement of 3D NAND flash memory in cyber-physical systems.
J. Syst. Archit., 2020
ApproxRefresh: Enabling Uncorrectable Data Reuse on Flash Memory with Approximate Read Awareness.
Proceedings of the 21st ACM SIGPLAN/SIGBED International Conference on Languages, 2020
MLCache: A Space-Efficient Cache Scheme based on Reuse Distance and Machine Learning for NVMe SSDs.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Exploiting Disturbance-Aware Read Redirection for Performance Improvement in 3D Flash Memory.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
2018
DLV: Exploiting Device Level Latency Variations for Performance Improvement on Flash Memory Storage Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
ShadowGC: Cooperative garbage collection with multi-level buffer for performance improvement in NAND flash-based SSDs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2016
Accelerating master-slave databases launched on LDPC-induced solid state drives with improved efficiency and reliability.
IEICE Electron. Express, 2016
Exploiting Cross-Layer Hotness Identification to Improve Flash Memory System Performance.
Proceedings of the Network and Parallel Computing, 2016
Proceedings of the Network and Parallel Computing, 2016
Proceedings of the 32nd Symposium on Mass Storage Systems and Technologies, 2016
2014
PT-LRU: a probabilistic page replacement algorithm for NAND flash-based consumer electronics.
IEEE Trans. Consumer Electron., 2014
Proceedings of the 14th IEEE International Conference on Computer and Information Technology, 2014