Jingyang Zhu
Orcid: 0000-0002-6370-2769
According to our database1,
Jingyang Zhu
authored at least 20 papers
between 2014 and 2024.
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Bibliography
2024
IEEE Trans. Wirel. Commun., October, 2024
Latency Minimization for Wireless Federated Learning With Heterogeneous Local Model Updates.
IEEE Internet Things J., January, 2024
Adaptive output dynamic feedback control for nonaffine pure-feedback time delay system with unknown backlash-like hysteresis.
J. Frankl. Inst., 2024
CoRR, 2024
2023
Tight Compression: Compressing CNN Through Fine-Grained Pruning and Weight Permutation for Efficient Implementation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023
Latency Minimization for Wireless Federated Learning with Heterogeneous Local Updates.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2023
Proceedings of the 4th International Conference on Machine Learning and Computer Application, 2023
Proceedings of the IEEE Globecom Workshops 2023, 2023
2021
Proceedings of the ICC 2021, 2021
2020
Tight Compression: Compressing CNN Model Tightly Through Unstructured Pruning and Simulated Annealing Based Permutation.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
SubMac: Exploiting the subword-based computation in RRAM-based CNN accelerator for energy saving and speedup.
Integr., 2019
CompRRAE: RRAM-based convolutional neural network accelerator with reduced computations through a runtime activation estimation.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
SparseNN: An energy-efficient neural network accelerator exploiting input and output sparsity.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
A high-throughput and energy-efficient RRAM-based convolutional neural network using data encoding and dynamic quantization.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
基于R-C模型的微博社区用户影响力分析 (Analysis of Microblog Community Users' Influence Based on R-C Model).
计算机科学, 2017
BHNN: A memory-efficient accelerator for compressing deep neural networks with blocked hashing techniques.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
BiLink: A high performance NoC router architecture using bi-directional link with double data rate.
Integr., 2016
LRADNN: High-throughput and energy-efficient Deep Neural Network accelerator using Low Rank Approximation.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2014
Proceedings of the 2014 IEEE International Conference on Data Mining Workshops, 2014